AM4376 datasheet(182/261 Pages) TI

182 / 261 page

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

5.12.8.2.1.3.9 DDR3 Net Classes

Table 5-57 lists the clock net classes for the DDR3 interface. Table 5-58 lists the signal net classes, and

associated clock net classes, for signals in the DDR3 interface. These net classes are used for the termination

and routing rules that follow.

Table 5-57. Clock Net Class Definitions

CLOCK NET CLASS

PIN NAMES

DDR_CK and DDR_CKn

DQS0

DDR_DQS0 and DDR_DQSn0

DQS1

DDR_DQS1 and DDR_DQSn1

DQS2

DDR_DQS2 and DDR_DQSn2

DQS3

DDR_DQS3 and DDR_DQSn3

Table 5-58. Signal Net Class Definitions

ASSOCIATED CLOCK

SIGNAL NET CLASS

PIN NAMES

NET CLASS

ADDR_CTRL

DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CSn1, DDR_CASn,

DDR_RASn, DDR_WEn, DDR_CKE0, DDR_CKE1, DDR_ODT0,

DDR_ODT1

DQ0

DQS0

DDR_D[7:0], DDR_DQM0

DQ1

DQS1

DDR_D[15:8], DDR_DQM1

DQ2

DQS2

DDR_D[23:16], DDR_DQM2

DQ3

DQS3

DDR_D[31:24], DDR_DQM3

5.12.8.2.1.3.10 DDR3 Signal Termination

Signal terminations are required for the CK and ADDR_CTRL net class signals. On-device terminations (ODTs)

are required on the DQS[x] and DQ[x] net class signals. Detailed termination specifications are covered in the

routing rules in the following sections.

Figure 5-50 provides an example DDR3 schematic with one 16-bit DDR3 memory device that does not have VTT

termination on the address and control signals. A typical DDR3 point-to-point topology may provide acceptable

signal integrity without VTT termination. System performance should be verified by performing signal integrity

analysis using specific PCB design details before implementing this topology.

5.12.8.2.1.3.11 DDR3 DDR_VREF Routing

DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the device.

DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with a voltage

divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide trace with 0.1

µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodate routing

congestion.

5.12.8.2.1.3.12 DDR3 VTT

Like DDR_VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike DDR_VREF, VTT

is expected to source and sink current, specifically the termination current for the ADDR_CTRL net class

Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power sub-

plane. VTT should be bypassed near the terminator resistors.

182

Specifications

Submit Documentation Feedback

Product Folder Links: AM4376 AM4377 AM4378 AM4379

AM4376 Datasheet(PDF) 182 Page - Texas Instruments

AM4376 Datasheet(HTML) 182 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL