AM4376 datasheet(212/261 Pages) TI

212 / 261 page

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

Table 5-79. DSS Register Configuration—RFBI Mode—Pico DLP (continued)

DESCRIPTION

BIT

VALUES

RE signal assertion time from Start Access

RFBI_ONOFF_TIMEi and

[23:20]

0b0000

Time

REOnTime

RE signal de-assertion time from Start Access

RFBI_ONOFF_TIMEi and

[29:24]

0b0000

Time

REOffTime

Write cycle time

RFBI_CYCLE_TIMEi and

[5:0]

0b000100: 4 cycles

WECycleTime

Read cycle time

RFBI_CYCLE_TIMEi and

[11:6]

0b000000

ReCycleTime

CS pulse width

RFBI_CYCLE_TIMEi and

[17:12]

0b000000

CSPulseWidth

Read to Write CS pulse width enable

RFBI_CYCLE_TIMEi and

[18]

0b0

RWEnable

Read to Read CS pulse width enable

RFBI_CYCLE_TIMEi and

[19]

0b0

RREnable

Write to Write CS pulse width enable

RFBI_CYCLE_TIMEi and

[20]

0b0

WWEnable

Write to Read CS pulse width enable

RFBI_CYCLE_TIMEi and

[21]

0b0

WREnable

From Start Access Time to CLK rising edge

RFBI_CYCLE_TIMEi and

[27:22]

0b000000

used for the first data capture

AccessTime

(1) i is equal to 0 or 1. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual

(SPRUHL7).

212

Specifications

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