AM4376 datasheet(215/261 Pages) TI

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AM4376, AM4377, AM4378, AM4379

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SPRS851B – JUNE 2014 – REVISED APRIL 2015

5.12.10 Camera (VPFE)

The camera (VPFE) controller receives input video/image data from external capture devices and stores it to

external memory which is transferred into the external memory via a built-in DMA engine. An internal buffer block

provides a high bandwidth path between the module and the external memory. The Cortex-A9 will process the

image data based on application requirements.

5.12.10.1 Camera (VPFE) Timing

The following tables assume testing over recommended operating conditions.

Table 5-81. VPFE Timing Requirements

1.8V, 3.3V

NO.

OPP50

OPP100

UNIT

MIN

MAX

MIN

MAX

VF1

tc(CAMx_CLK)

Cycle time, pixel clock input, CAMx_CLK

13.3

tsu(CAMx_D-

VF2

Setup time, CAMx_D to CAMx_CLK rising edge

7.5

3.5

CAMx_CLK)

tsu(CAMx_HD-

VF3

Setup time, CAMx_HD to CAMx_CLK rising edge

7.5

3.5

CAMx_CLK)

tsu(CAMx_VD-

VF4

Setup time, CAMx_VD to CAMx_CLK rising edge

7.5

3.5

CAMx_CLK)

tsu(CAMx_WEN-

VF5

Setup time, CAMx_WEN to CAMx_CLK rising edge

7.5

3.5

CAMx_CLK)

VF6

tsu(C_FLD-CAMx_CLK) Setup time, CAMx_FIELD to CAMx_CLK rising edge

7.5

3.5

th(CAMx_CLK-

VF7

Hold time, CAMx_D valid after CAMx_CLK rising edge

6.5

2.5

CAMx_D)

th(VDIN-HD-

VF8

Hold time, CAMx_HD to CAMx_CLK rising edge

6.5

2.5

CAMx_CLK)

th(CAMx_VD-

VF9

Hold time, CAMx_VD to CAMx_CLK rising edge

6.5

2.5

CAMx_CLK)

th(CAMx_WEN-

VF10

Hold time, CAMx_WEN to CAMx_CLK rising edge

6.5

2.5

CAMx_CLK)

VF11 th(C_FLD-CAMx_CLK)

Hold time, CAMx_FIELD to CAMx_CLK rising edge

6.5

2.5

Table 5-82. VPFE Output Switching Characteristics

1.8V, 3.3V

NO.

PARAMETER

OPP50

OPP100

UNIT

MIN

MAX

MIN

MAX

td(CAMx_HD-

VF12

Output delay time, CAMx_HD to CLK rising edge

CAMx_CLK)

td(CAMx_VD-

VF13

Output delay time, CAMx_VD to CLK rising edge

CAMx_CLK)

td(CAMx_WEN-

VF14

Output delay time, CAMx_WEN to CLK rising edge

CAMx_CLK)

Specifications

215

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