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AM4376 Datasheet(PDF) 217 Page - Texas Instruments |
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AM4376 Datasheet(HTML) 217 Page - Texas Instruments |
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217 / 261 page  AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851B – JUNE 2014 – REVISED APRIL 2015 5.12.11 Inter-Integrated Circuit (I2C) For more information, see the Inter-Integrated Circuit (I2C) section of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual (SPRUHL7). 5.12.11.1 I2C Electrical Data and Timing Table 5-83. I2C Timing Conditions - Slave Mode STANDARD MODE FAST MODE TIMING CONDITION PARAMETER UNIT MIN MAX MIN MAX Output Condition Cb Capacitive load for each bus line 400 400 pF Table 5-84. Timing Requirements for I2C Input Timings (see Figure 5-102) STANDARD MODE FAST MODE NO. UNIT MIN MAX MIN MAX 1 tc(SCL) Cycle time, SCL 10 2.5 us Setup Time, SCL high before SDA low (for a repeated 2 tsu(SCLH-SDAL) 4.7 0.6 us START condition) Hold time, SCL low after SDA low (for a START and a 3 th(SDAL-SCLL) 4 0.6 us repeated START condition) 4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 us 5 tw(SCLH) Pulse duration, SCL high 4 0.6 us 6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100(1) ns 7 th(SCLL-SDAV) Hold time, SDA valid after SCL low 0(2) 3.45(3) 0(2) 0.9(3) us Pulse duration, SDA high between STOP and START 8 tw(SDAH) 4.7 1.3 us conditions 9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb(4) 300 ns 10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb(4) 300 ns 11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb(4) 300 ns 12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb(4) 300 ns 13 tsu(SCLH-SDAH) Setup time, high before SDA high (for STOP condition) 4 0.6 us 14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 0 50 ns (1) A fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the standard-mode I2C-Bus Specification) before the SCL line is released. (2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (4) Cb is line load in pF. Copyright © 2014–2015, Texas Instruments Incorporated Specifications 217 Submit Documentation Feedback Product Folder Links: AM4376 AM4377 AM4378 AM4379 |
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