AM4376 datasheet(208/261 Pages) TI

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SWPS038-056

dss_pclk

dss_vsync

dss_hsync

dss_acbias

dss_data[23:0]

DL4

DL5

DL3

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

Table 5-74. DSS Switching Characteristics—STN Mode(1) (continued)

OPP100

OPP50

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

DL5

tw(pclk)

Pulse duration, output pixel clock dss_pclk low or high

0.45P(3)

0.55P(3)(4)

0.45P(3)

0.55P(3)(4)

tJ(pclk)

Peak-peak jitter, output pixel clock dss_pclk

200

(3)

P = dss_pclk period in ns

(4)

tW(pclk) = 0.66P when DISPC_DIVISOR[7:0] PCD = 3

The pixel data bus depends on the use of 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of

dss_pclk too.

dss_vsync width must be programmed to be as small as possible.

The pixel clock frequency is programmable.

For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual

(SPRUHL7).

Figure 5-94. DSS—STN Mode

5.12.9.1.2 DSS—Parallel Interface—RFBI Mode—Applications

5.12.9.1.2.1 DSS—Parallel Interface—RFBI Mode—MIPI DBI 2.0—LCD Panel

The Remote Frame Buffer Interface (RFBI) module provides the necessary control signals and data (MIPI® DBI

2.0 type B protocol) to interface to the LCD driver of the LCD panel.

Table 5-76 and Table 5-77 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 5-95 through Figure 5-97).

Table 5-75. DSS Timing Conditions—RFBI Mode—MIPI DBI 2.0—LCD Panel(1)

VALUE

TIMING CONDITION PARAMETER

UNIT

MIN

MAX

Input Conditions

Input signal rise time

Input signal fall time

Output Condition

CLOAD

Output load capacitance

(1)

For any information regarding the RFBI registers configuration, see the Display Subsystem / Display Subsystem Environment / LCD

Support / Parallel Interface / Parallel Interface in RFBI Mode (MIPI DBI Protocol) / Transaction Timing Diagrams section of the AM437x

Sitara Processors Technical Reference Manual (SPRUHL7).

208

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