AM4376 datasheet(207/261 Pages) TI

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SWPS038-055

dss_pclk

dss_vsync

dss_hsync

dss_acbias

dss_data[23:0]

DL4

DL5

DL3

DL0

DL2

DL1

AM4376, AM4377, AM4378, AM4379

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SPRS851B – JUNE 2014 – REVISED APRIL 2015

Table 5-72. DSS Switching Characteristics—TFT Mode (continued)

OPP100

OPP50

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

DL5

tw(pclk)

Pulse duration, output pixel clock dss_pclk low or high

0.45P(2)

0.55P(2)(3)

0.45P(2)

0.55P(2)(3)

tJ(pclk)

Peak-peak jitter, output pixel clock dss_pclk

200

(1) The pixel clock frequency is software programmable via the pixel clock DISPC_DIVISOR register.

(2) P = dss_pclk period in ns

(3) tw(pclk) = 0.66P when DISPC_DIVISOR[7:0] PCD = 3

The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

The pixel clock frequency is programmable.

All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of

dss_pclk too.

For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual

(SPRUHL7).

Figure 5-93. DSS—TFT Mode

5.12.9.1.1.2 DSS—Parallel Interface—Bypass Mode—STN Mode

Table 5-74 assumes testing over the recommended operating conditions and electrical characteristic conditions

below (see Figure 5-94).

Table 5-73. DSS Timing Conditions—STN Mode

VALUE

TIMING CONDITION PARAMETER

UNIT

MIN

MAX

Output Condition

CLOAD

Output load capacitance

Table 5-74. DSS Switching Characteristics—STN Mode(1)

OPP100

OPP50

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

DL3

td(pclkA-dV)

Delay time, output pixel clock dss_pclk active edge to

-6

output data dss_data[7:0] valid

DL4

1 / tc(pclk)

Frequency(2), output pixel clock dss_pclk

MHz

(1)

The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.

(2)

The pixel clock frequency is software programmable via the pixel clock divider DISPC_DIVISOR register.

Specifications

207

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