AM4376 datasheet(203/261 Pages) TI

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DQLMYi

DQi

DQLMXi

i = 0, 1, 2, 3

LPDDR2

interface

DQLM0 = DQLMX0 + DQLMY0

DQLM2 = DQLMX2 + DQLMY2

DQLM3 = DQLMX3 + DQLMY3

DQLM1 = DQLMX1 + DQLMY1

DQ0 - DQ3 represent data bytes 0 - 3.

AM4376, AM4377, AM4378, AM4379

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SPRS851B – JUNE 2014 – REVISED APRIL 2015

There are four DQLMs, one for each data byte, in a 32-bit interface and two DQLMs, one for each data byte, in a 16-

bit interface. Each DQLM is the longest Manhattan distance of the byte.

Figure 5-87. DQLM for LPDDR2 Interface

Trace routing specifications for the DQ[x] and the DQS[x] are specified in Table 5-69.

Table 5-69. DQS[x] and DQ[x] Routing Specification(1)(2)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

DQ0 nominal length(3)(4)

DQLM0

mils

DQ1 nominal length(3)(5)

DQLM1

mils

DQ2 nominal length (3)(6)

DQLM2

mils

DQ3 nominal length (3)(7)

DQLM3

mils

DQ[x] skew(8)

mils

DQS[x] skew

mils

Via count per each trace in DQ[x], DQS[x]

Via count difference across a given DQ[x], DQS[x]

DQS[x]-to-DQ[x] skew(8)(9)

mils

Center-to-center DQ[x] to other LPDDR2 trace spacing(10)(11)

Center-to-center DQ[x] to other DQ[x] trace spacing(10)(12)

DQS[x] center-to-center spacing(13)

DQS[x] center-to-center spacing to other net(10)

(1) DQS[x] represents the DQS0, DQS1, DQS2, DQS3 clock net classes, and DQ[x] represents the DQ0, DQ1, DQ2, DQ3 signal net

classes.

(2) External termination disallowed. Data termination should use built-in ODT functionality.

(3) DQLMn is the longest Manhattan distance of a byte.

(4) DQLM0 is the longest Manhattan length for the DQ0 net class.

(5) DQLM1 is the longest Manhattan length for the DQ1 net class.

(6) DQLM2 is the longest Manhattan length for the DQ2 net class.

(7) DQLM3 is the longest Manhattan length for the DQ3 net class.

(8) Length matching is only done within a byte. Length matching across bytes is not required.

(9) Each DQS clock net class is length matched to its associated DQ signal net class.

(10) Center-to-center spacing is allowed to fall to minimum for up to 1000 mils of routed length.

(11) Other LPDDR2 trace spacing means signals that are not part of the same DQ[x] signal net class.

(12) This applies to spacing within same DQ[x] signal net class.

(13) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-

ended impedance.

Specifications

203

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