AM4376 datasheet(199/261 Pages) TI

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AM4376, AM4377, AM4378, AM4379

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SPRS851B – JUNE 2014 – REVISED APRIL 2015

5.12.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices

Table 5-63 shows the supported LPDDR2 device configurations which are compatible with this interface.

Table 5-63. Compatible JEDEC LPDDR2 Devices (Per Interface)

NO.

PARAMETER

CONDITION

MIN

MAX

UNIT

JEDEC LPDDR2 device speed grade

tc(DDR_CK) and tc(DDR_CKn)

LPDDR2-533

JEDEC LPDDR2 device bit width

x16

x32

Bits

JEDEC LPDDR2 device count

2(1)

Devices

(1) Two devices are supported only with twin-die configuration which embeds two devices in the same package.

5.12.8.2.2.3.3 LPDDR2 PCB Stackup

Table 5-64 shows the minimum stackup requirements. Additional layers may be added to the PCB stackup to

accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to

reduce the size of the PCB footprint.

Table 5-64. Minimum PCB Stackup

LAYER

TYPE

DESCRIPTION

Signal

Top signal routing

Plane

Ground

Plane

Power

Signal

Bottom signal routing

PCB stackup specifications for LPDDR2 interface are listed in Table 5-65.

Table 5-65. PCB Stackup Specifications(1)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

PCB routing and plane layers

Signal routing layers

Full ground reference layers under LPDDR2 routing region(1)

Full VDDS_DDR power reference layers under the LPDDR2 routing

region(1)

Number of reference plane cuts allowed within LPDDR2 routing region(2)

Number of layers between LPDDR2 routing layer and reference plane(3)

PCB routing feature size

mils

PCB trace width, w

mils

PCB BGA escape via pad size(4)

mils

PCB BGA escape via hole size

mils

Single-ended impedance, Zo(5)

ohms

Impedance control(6)(7)

Zo-5

Zo+5

ohms

(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer

return current as the trace routes switch routing layers.

(2) No traces should cross reference plane cuts within the LPDDR2 routing region. High-speed signal traces crossing reference plane cuts

create large return current paths which can lead to excessive crosstalk and EMI radiation.

(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.

(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available

for power routing. An 18-mil pad is required for minimum layer count escape.

(5) Zo is the nominal singled-ended impedance selected for the PCB.

(6) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo

defined by the single-ended impedance parameter.

(7) Tighter impedance control is required to ensure flight time skew is minimal.

Specifications

199

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