AM4376 datasheet(195/261 Pages) TI

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DQLMY0

DQLMX1

DQ1

DQ0

DQLMX0

DQ[8:15], DM1, DQS1

DQ[0:7], DM0, DQS0

DQLMY1

DQ0 - DQ3 represent data bytes 0 - 3.

DQ2

DQ[16:23], DM2, DQS2

DQLMX2

DQ3

DQ[24:31], DM3, DQS3

DQLMX3

DQLMY3 DQLMY2

AM4376, AM4377, AM4378, AM4379

www.ti.com

SPRS851B – JUNE 2014 – REVISED APRIL 2015

There are four DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the

byte; therefore:

DQLM0 = DQLMX0 + DQLMY0

DQLM1 = DQLMX1 + DQLMY1

DQLM2 = DQLMX2 + DQLMY2

DQLM3 = DQLMX3 + DQLMY3

Figure 5-77. DQLM for Any Number of Allowed DDR3 Devices

Table 5-60. DQS[x] and DQ[x] Routing Specification(1)(2)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

DQ0 nominal length(3)(4)

DQLM0

mils

DQ1 nominal length(3)(5)

DQLM1

mils

DQ2 nominal length

DQLM2

mils

DQ3 nominal length

DQLM3

mils

DQ[x] skew(6)

mils

DQS[x] skew

mils

DQS[x]-to-DQ[x] skew(6)(7)

mils

Center-to-center DQ[x] to other DDR3 trace spacing(8)(9)

Center-to-center DQ[x] to other DQ[x] trace spacing(8)(10)

DQS[x] center-to-center spacing(11)

DQS[x] center-to-center spacing to other net(8)

(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.

(2) External termination disallowed. Data termination should use built-in ODT functionality.

(3) DQLMn is the longest Manhattan distance of a byte. For definition, see Section 5.12.8.2.1.6.2 and Figure 5-77.

(4) DQLM0 is the longest Manhattan length for the DQ0 net class.

(5) DQLM1 is the longest Manhattan length for the DQ1 net class.

(6) Length matching is only done within a byte. Length matching across bytes is not required. To maintain tighter delay skew, route the

DQ[x] and DQS[x] signals within a byte to have same number of VIA and layer transitions.

(7) Each DQS clock net class is length matched to its associated DQ signal net class.

(8) Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.

(9) Other DDR3 trace spacing means signals that are not part of the same DQ[x] signal net class.

(10) This applies to spacing within same DQ[x] signal net class.

(11) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-

ended impedance defined in Table 5-53.

Specifications

195

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