AM4376 datasheet(194/261 Pages) TI

194 / 261 page

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

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Table 5-59. CK and ADDR_CTRL Routing Specification(1)(2)(3) (continued)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

A4 length

660

mils

A4 skew

mils

AS length

100

mils

AS skew

mils

AS+ and AS- length

mils

AS+ and AS- skew

mils

AT length(6)

500

mils

AT skew(7)

100

mils

AT skew(8)

mils

CK and ADDR_CTRL nominal trace length(9)

CACLM-50

CACLM

CACLM+50

mils

Center-to-center CK to other DDR3 trace spacing(10)

Center-to-center ADDR_CTRL to other DDR3 trace spacing(10)(11)

Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(10)

CK center-to-center spacing(12)

CK spacing to other net(10)

Rcp(13)

Zo-1

Zo+1

ohms

Rtt(13)(14)

Zo-5

Zo+5

ohms

(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.

(2) The use of vias should be minimized.

(3) Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump

between the VDDS_DDR plane and the ground plane when the net class switches layers at a via.

(4) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).

(5) Non-mirrored configuration (all DDR3 memories on same side of PCB).

(6) While this length can be increased for convenience, its length should be minimized.

(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.

(8) CK net class only.

(9) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 5.12.8.2.1.6.1

and Figure 5-76.

(10) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.

(11) Signals from one DQ net class should be considered other DDR3 traces to another DQ net class.

(12) CK spacing set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-ended

impedance defined in Table 5-53.

(13) Source termination (series resistor at driver) is specifically not allowed.

(14) Termination values should be uniform across the net class.

5.12.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification

Skew within the DQS[x] and DQ[x] net classes directly reduces setup and hold margin and, thus, this skew must

be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the

length of the longest net in the net class and its associated clock. DQLMn is defined as DQ Longest Manhattan

distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

NOTE

It is not required, nor is it recommended, to match the lengths across all bytes. Length matching is

only required within each byte.

Given the DQS[x] and DQ[x] pin locations on the device and the DDR3 memories, the maximum possible

Manhattan distance can be determined given the placement. Figure 5-77 shows this distance for a two-load

case. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are

determined. For DQS[x] and DQ[x] routing, these specifications are contained in Table 5-60.

194

Specifications

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