AM4376 datasheet(196/261 Pages) TI

196 / 261 page

DDR_CK

DDR_CKn

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

5.12.8.2.2 LPDDR2 Routing Guidelines

This section provides the timing specification for the LPDDR2 interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and

signal timing. These rules, when followed, result in a reliable LPDDR2 memory system without the need for a

complex timing closure process. For more information regarding guidelines for using this LPDDR2 specification,

see the Understanding TI's PCB Routing Rule-Based DDR Timing Specification application report (SPRAAV0).

This application report provides generic guidelines and approach. All the specifications provided in the data

manual take precedence over the generic guidelines and must be adhered to for a reliable LPDDR2 interface

operation.

5.12.8.2.2.1 LPDDR2 Board Designs

TI only supports board designs using LPDDR2 memory that follow the guidelines in this document. The switching

characteristics and timing diagram for the LPDDR2 memory interface are shown in Table 5-61 and Figure 5-78.

Table 5-61. Switching Characteristics for LPDDR2 Memory Interface

NO.

PARAMETER

MIN

MAX

UNIT

tc(DDR_CK)

Cycle time, DDR_CK and DDR_CKn

7.52

3.76(1)

(1) The JEDEC JESD209-2F standard defines the maximum clock period of 100 ns for all standard-speed bin LPDDR2 memory. The

device has only been tested per the limits published in this table.

Figure 5-78. LPDDR2 Memory Interface Clock Timing

5.12.8.2.2.2 LPDDR2 Device Configurations

There are several possible combinations of device counts and single-side or dual-side mounting. Table 5-62 lists

all the supported configurations.

Table 5-62. Supported LPDDR2 Device Combinations

NUMBER OF LPDDR2

LPDDR2 DEVICE WIDTH (BITS)

MIRRORED?(1)

LPDDR2 EMIF WIDTH (BITS)

DEVICES

2(2)

(1) Two LPDDR2 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of

the board.

(2) Two devices are supported only with twin-die configuration which embeds two devices in the same package.

Details on treating unused pins are listed in Section 5.12.8.2.2.3.1.

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