AM4376 datasheet(200/261 Pages) TI

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LPDDR2 Keepout Region

Encompasses Entire

LPDDR2 Routing Area

LPDDR2

interface

LPDDR2

interface

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

5.12.8.2.2.3.4 LPDDR2 Placement

Figure 5-81 shows the placement rules for the device as well as the LPDDR2 memory device. Placement

restrictions are provided as a guidance to restrict maximum trace lengths and allow for proper routing space.

Figure 5-81. Placement Specifications

Table 5-66. Placement Specifications(1)

NO.

PARAMETER

MIN

MAX

UNIT

X1 Offset(2)(3)

1500

mils

Y Offset(2)(3)(4)

1500

mils

Clearance from non-LPDDR2 signal to LPDDR2 keepout region(4)(5)

(1) LPDDR2 keepout region to encompass entire LPDDR2 routing area.

(2) Measurements from center of device to center of LPDDR2 device.

(3) Minimizing X1 and Y improves timing margins.

(4) w is defined as the signal trace width.

(5) Non-LPDDR2 signals allowed within LPDDR2 keepout region provided they are separated from LPDDR2 routing layers by a ground

plane.

5.12.8.2.2.3.5 LPDDR2 Keepout Region

The region of the PCB used for LPDDR2 circuitry must be isolated from other signals. The LPDDR2 keepout

region is defined for this purpose and is shown in Figure 5-82. This region should encompass all LPDDR2

circuitry and the region size varies with component placement and LPDDR2 routing. Non-LPDDR2 signals should

not be routed on the same signal layer as LPDDR2 signals within the LPDDR2 keepout region. Non-LPDDR2

signals may be routed in the region provided they are routed on layers separated from LPDDR2 signal layers by

a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region.

In addition, the VDDS_DDR power plane should cover the entire keepout region.

Figure 5-82. LPDDR2 Keepout Region

200

Specifications

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