AM4376 datasheet(201/261 Pages) TI

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Device

DQS[x]

IO Buffer

DDR3

DQS[x]

IO Buffer

Routed Differentially

DQS[x]-

DQS[x]+

AM4376, AM4377, AM4378, AM4379

www.ti.com

SPRS851B – JUNE 2014 – REVISED APRIL 2015

5.12.8.2.2.3.6 LPDDR2 Net Classes

Table 5-67. Clock Net Class Definitions for the LPDDR2

Interface

CLOCK NET CLASS

PIN NAMES

DDR_CK and DDR_CKn

DQS0

DDR_DQS0 and DDR_DQSn0

DQS1

DDR_DQS1 and DDR_DQSn1

DQS2

DDR_DQS2 and DDR_DQSn2

DQS3

DDR_DQS3 and DDR_DQSn3

Table 5-68. Signal Net Class and Associated Clock Net Class for LPDDR2 Interface

ASSOCIATED CLOCK

SIGNAL NET CLASS

PIN NAMES

NET CLASS

ADDR_CTRL

DDR_BA[2:0], DDR_CSn0, DDR_CSn1, DDR_CKE0, DDR_CKE1,

DDR_RASn, DDR_CASn, DDR_WEn, DDR_A1, DDR_A2, DDR_A10,

DDR_A13

DQ0

DQS0

DDR_D[7:0], DDR_DQM0

DQ1

DQS1

DDR_D[15:8], DDR_DQM1

DQ2

DQS2

DDR_D[23:16], DDR_DQM2

DQ3

DQS3

DDR_D[31:24], DDR_DQM3

5.12.8.2.2.3.7 LPDDR2 Signal Termination

On-device termination (ODT) is available for DQ[3:0] signal net classes, but is not specifically required for normal

operation. System designers may evaluate the need for additional series termination if required based on signal

integrity, EMI and overshoot/undershoot reduction.

5.12.8.2.2.3.8 LPDDR2 DDR_VREF Routing

DDR_VREF is the reference voltage for the input buffers on the LPDDR2 memory as well as the device.

DDR_VREF is intended to be half the LPDDR2 power supply voltage and is typically generated with a voltage

divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide trace with 0.1-

µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodate routing

congestion.

5.12.8.2.2.4 Routing Specification

DQS[x] and DQ[x] Routing Specification

DQS[x] lines are point-to-point differential and DQ[x] lines are point-to-point single ended. Figure 5-83 and

Figure 5-84 represent the supported topologies. Figure 5-85 and Figure 5-86 show the DQS[x] and DQ[x] routing.

Figure 5-87 shows the DQLM for the LPDDR2 interface.

x = 0, 1, 2, 3

Figure 5-83. DQS[x] Topology

Specifications

201

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