AM4376 datasheet(206/261 Pages) TI

206 / 261 page

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

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5.12.9 Display Subsystem (DSS)

NOTE

For more information, see the Display Subsystem chapter of the AM437x Sitara Processors

Technical Reference Manual (SPRUHL7).

The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or internal

(SRAM) memory on an LCD panel or a TV set. The display subsystem integrates the following elements:

•

Display controller (DISPC) module

•

Remote frame buffer interface (RFBI) module

The DSS can be used in the following configuration: LCD display with parallel interface

5.12.9.1 DSS—Parallel Interface

In parallel interface, the paths of the display subsystem modules are the display controller and the RFBI. The

display controller has two I/O pad modes and could be in the following configuration:

•

Bypass mode (RFBI disabled), which implements the MIPI DPI protocol

•

RFBI mode (RFBI enabled), which implements MIPI DBI 2.0 type B protocol

5.12.9.1.1 DSS—Parallel Interface—Bypass Mode

Two types of LCD panel are supported:

•

Thin film transistor (TFT) or active matrix technology

•

Supertwisted nematic (STN) or passive matrix technology

Both configurations are discussed in the following paragraphs.

5.12.9.1.1.1 DSS—Parallel Interface—Bypass Mode—TFT Mode

Table 5-72 assumes testing over the recommended operating conditions and electrical characteristic conditions

below (see Figure 5-93).

Table 5-71. DSS Timing Conditions—TFT Mode

VALUE

TIMING CONDITION PARAMETER

UNIT

MIN

MAX

Output Condition

CLOAD

Output load capacitance

Table 5-72. DSS Switching Characteristics—TFT Mode

OPP100

OPP50

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

DL0

td(pclkA-hsync)

Delay time, output pixel clock dss_pclk active edge to

-2.4

2.4

-3.5

2.5

output horizontal synchronization dss_hsync transition

DL1

td(pclkA-vsync)

Delay time, output pixel clock dss_pclk active edge to

-2.4

2.4

-3.5

2.5

output vertical synchronization dss_vsync transition

DL2

td(pclkA-acbiasA)

Delay time, output pixel clock dss_pclk active edge to

-2.4

2.4

-3.5

2.5

output data enable dss_acbias active level

DL3

td(pclkA-dV)

Delay time, output pixel clock dss_pclk active edge to

-2.4

2.4

-3.5

2.5

output data dss_data[23:0] valid

DL4

1 / tc(pclk)

Frequency(1), output pixel clock dss_pclk

100

MHz

206

Specifications

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