AM5728 datasheet(206/415 Pages) TI

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rtc_osc_xi_clkin32

CK0

CK1

Device

rtc_osc_xo

rtc_osc_xi_clkin32

SPRS85v_CLK_11

AM5728, AM5726

SPRS915O – MARCH 2014 – REVISED OCTOBER 2015

www.ti.com

6.1.4.2

RTC Oscillator Input Clock

A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the

SYS_32K clock input to the system. The external connections to support this are shown in Figure 6-12.

The rtc_osc_xi_clkin32 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The rtc_osc_xo

pin is left unconnected.

Figure 6-12. LVCMOS-Compatible Clock Input

Table 6-11 summarizes the RTC Oscillator input clock electrical characteristics.

Table 6-11. RTC Oscillator Input Clock Electrical Characteristics—Bypass Mode

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency

32.768

kHz

Input capacitance

2.178

2.378

2.578

Input current (3.3V mode)

µA

tsX

Start-up time

See (1)

(1) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is

inapplication mode and receives a wave. The switching time in this case is about 100

μs.

Figure 6-13. rtc_osc_xi_clkin32 Input Clock

6.2

DPLLs, DLLs Specifications

NOTE

For more information, see:

•

Power, Reset, and Clock Management / Clock Management Functional / Internal Clock

Sources and Generators / Generic DPLL Overview section

and

•

Display Subsystem / Display Subsystem Overview section of the Device TRM.

To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the

PRCM module. They are of two types: type A and type B DPLLs.

•

They have their own independent power domain (each one embeds its own switch and can be

controlled as an independent functional power domain)

•

They are fed with ALWAYS ON system clock, with independent control per DPLL.

206

Clock Specifications

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