AM5728 datasheet(208/415 Pages) TI

208 / 415 page

AM5728, AM5726

SPRS915O – MARCH 2014 – REVISED OCTOBER 2015

www.ti.com

For more information, see the Power, Reset, and Clock Management chapter of the Device TRM.

Table 6-12 summarizes DPLL type described in Section 6.2, DPLLs, DLLs Specifications introduction.

Table 6-12. DPLL Control Type

DPLL NAME

TYPE

CONTROLLED BY PRCM

DPLL_ABE

Table 6-13 (Type A)

Yes(1)

DPLL_CORE

Table 6-13 (Type A)

Yes(1)

DPLL_DEBUGSS

Table 6-13 (Type A)

No(2)

DPLL_DSP

Table 6-13 (Type A)

Yes(1)

DPLL_GMAC

Table 6-13 (Type A)

Yes(1)

DPLL_HDMI

Table 6-14 (Type B)

No(2)

DPLL_IVA

Table 6-13 (Type A)

Yes(1)

DPLL_MPU

Table 6-13 (Type A)

Yes(1)

DPLL_PER

Table 6-13 (Type A)

Yes(1)

APLL_PCIE

Table 6-13 (Type A)

Yes(1)

DPLL_PCIE_REF

Table 6-14 (Type B)

Yes(1)

DPLL_SATA

Table 6-14 (Type B)

No(2)

DPLL_USB

Table 6-14 (Type B)

Yes(1)

DPLL_USB_OTG_SS

Table 6-14 (Type B)

No(2)

DPLL_VIDEO1

Table 6-13 (Type A)

No(2)

DPLL_VIDEO2

Table 6-13 (Type A)

No(2)

DPLL_DDR

Table 6-13 (Type A)

Yes(1)

DPLL_GPU

Table 6-13 (Type A)

Yes(1)

(1) DPLL is in the always-on domain.

(2) DPLL is not controlled by the PRCM.

Table 6-13 and Table 6-14 summarize the DPLL characteristics and assume testing over recommended

operating conditions.

Table 6-13. DPLL Type A Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

COMMENTS

finput

CLKINP input frequency

0.032

MHz

FINP

finternal

Internal reference frequency

0.15

MHz

REFCLK

fCLKINPHIF

CLKINPHIF input frequency

1400

MHz

FINPHIF

Bypass mode: fCLKOUT =

fCLKINPULOW

CLKINPULOW input frequency

0.001

600

MHz

fCLKINPULOW / (M1 + 1) if

ulowclken = 1(6)

[M / (N + 1)] × FINP × [1 / M2]

fCLKOUT

CLKOUT output frequency

20(1)

1400(2)

MHz

(in locked condition)

2 × [M / (N + 1)] × FINP × [1 /

fCLKOUTx2

CLKOUTx2 output frequency

40(1)

2200(2)

MHz

M2] (in locked condition)

20(3)

1400(4)

MHz

FINPHIF / M3 if clkinphifsel = 1

fCLKOUTHIF

CLKOUTHIF output frequency

2 × [M / (N + 1)] × FINP × [1 /

40(3)

2200(4)

MHz

M3] if clkinphifsel = 0

DCOCLKLDO output

2 × [M / (N + 1)] × FINP (in

fCLKDCOLDO

2800

MHz

frequency

locked condition)

6 + 350 ×

tlock

Frequency lock time

µs

REFCLK

6 + 500 ×

plock

Phase lock time

µs

REFCLK

Relock time—Frequency

6 + 70 ×

DPLL in LP relock time:

trelock-L

lock(5) (LP relock time from

µs

REFCLK

lowcurrstdby = 1

bypass)

208

Clock Specifications

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