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AM5728 Datasheet(PDF) 229 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 229 Page - Texas Instruments |
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229 / 415 page  AM5728, AM5726 www.ti.com SPRS915O – MARCH 2014 – REVISED OCTOBER 2015 Table 7-10. Manual Functions Mapping for VIP2 4A (continued) BAL BALL NAME VIP2_4A_MANUAL1 VIP2_4A_MANUAL2 CFG REGISTER MUXMODE L A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 3 4 5 C9 vout1_d20 2617 91 2979 0 CFG_VOUT1_D20_IN vin4a_d4 - - A9 vout1_d21 2103 0 2374 0 CFG_VOUT1_D21_IN vin4a_d5 - - B9 vout1_d22 2231 0 2501 0 CFG_VOUT1_D22_IN vin4a_d6 - - A10 vout1_d23 2314 38 2623 0 CFG_VOUT1_D23_IN vin4a_d7 - - G11 vout1_d3 2639 68 2977 0 CFG_VOUT1_D3_IN vin4a_d19 - - E9 vout1_d4 2645 0 2916 0 CFG_VOUT1_D4_IN vin4a_d20 - - F9 vout1_d5 2545 47 2861 0 CFG_VOUT1_D5_IN vin4a_d21 - - F8 vout1_d6 2620 0 2891 0 CFG_VOUT1_D6_IN vin4a_d22 - - E7 vout1_d7 2741 51 3062 1 CFG_VOUT1_D7_IN vin4a_d23 - - E8 vout1_d8 2636 113 3019 0 CFG_VOUT1_D8_IN vin4a_d8 - - D9 vout1_d9 2705 0 2976 0 CFG_VOUT1_D9_IN vin4a_d9 - - B10 vout1_de 2347 0 2618 0 CFG_VOUT1_DE_IN vin4a_de0 - - B11 vout1_fld 0 0 0 0 CFG_VOUT1_FLD_IN vin4a_clk0 - - C11 vout1_hsync 2036 0 2307 0 CFG_VOUT1_HSYNC_IN vin4a_hsync0 - - E11 vout1_vsync 1808 0 2079 0 CFG_VOUT1_VSYNC_IN vin4a_vsync0 - - Manual IO Timings Modes must be used to guaranteed some IO timings for VIP2. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-11 Manual Functions Mapping for VIP2 4A IOSET3 for a definition of the Manual modes. Table 7-11 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. Table 7-11. Manual Functions Mapping for VIP2 4A IOSET3 BALL BALL NAME VIP2_4A_IOSET3_MANUAL1 VIP2_4A_IOSET3_MANUAL2 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 8 E21 gpio6_14 1442 120 1839 180 CFG_GPIO6_14_IN vin4a_hsync0 F20 gpio6_15 1869 120 2266 120 CFG_GPIO6_15_IN vin4a_vsync0 F21 gpio6_16 1614 120 2012 180 CFG_GPIO6_16_IN vin4a_fld0 B14 mcasp1_aclkr 2572 120 2850 300 CFG_MCASP1_ACLKR_IN vin4a_d0 G13 mcasp1_axr2 3050 1160 2915 1760 CFG_MCASP1_AXR2_IN vin4a_d2 J11 mcasp1_axr3 3175 820 3100 1360 CFG_MCASP1_AXR3_IN vin4a_d3 E12 mcasp1_axr4 2950 990 2930 1560 CFG_MCASP1_AXR4_IN vin4a_d4 F13 mcasp1_axr5 3050 900 2910 1560 CFG_MCASP1_AXR5_IN vin4a_d5 C12 mcasp1_axr6 3140 600 3050 1200 CFG_MCASP1_AXR6_IN vin4a_d6 Copyright © 2014–2015, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 229 Submit Documentation Feedback Product Folder Links: AM5728 AM5726 |
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