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AM5728 Datasheet(PDF) 253 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 253 Page - Texas Instruments |
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253 / 415 page  gpmc_clk gpmc_csi gpmc_a[2 :1] 7 gpmc_ 1 ben gpmc_ben0 gpmc_ _ale advn gpmc_wen gpmc_ad[15:0] gpmc_waitj DIR Address D 0 D 1 D 2 D 3 OUT F4 F15 F15 F15 F1 F1 F2 F6 F8 F8 F0 F3 F17 F17 F17 F9 F6 F17 F17 F17 F18 F20 F14 F14 F22 F21 SPRS91v_GPMC_06 AM5728, AM5726 www.ti.com SPRS915O – MARCH 2014 – REVISED OCTOBER 2015 Figure 7-12. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits - (GpmcFCLKDivider = 0)(1)(2) (1) In gpmc_csi, i = 1 to 7. (2) In gpmc_waitj, j = 0 to 1. (3) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing CAUTION The IO Timings provided in this section are only valid for some GPMC usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section. Table 7-28 and Table 7-29 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-13, Figure 7-14, Figure 7-15, Figure 7-16, Figure 7-17, and Figure 7-18). Table 7-28. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT FA5 tacc(DAT) Data Maximum Access Time (GPMC_FCLK cycles) H (1) cycles FA20 tacc1-pgmode(DAT) Page Mode Successive Data Maximum Access Time (GPMC_FCLK P (2) cycles cycles) Copyright © 2014–2015, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 253 Submit Documentation Feedback Product Folder Links: AM5728 AM5726 |
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