AM5728 datasheet(256/415 Pages) TI

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GPMC_FCLK

gpmc_clk

gpmc_csi

gpmc_a[

:1]

gpmc_ben0

gpmc_be 1

gpmc_

_ale

advn

gpmc_oen_ren

gpmc_ d[15:0]

gpmc_waitj

DIR

Address 0

Address 1

Valid

Data Upper

OUT

FA9

FA10

FA3

FA9

FA3

FA13

FA1

FA4

FA12

FA10

FA0

FA16

FA0

FA10

FA5

FA14

FA15

FA14

FA15

GPMC_08

AM5728, AM5726

SPRS915O – MARCH 2014 – REVISED OCTOBER 2015

www.ti.com

Figure 7-14. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing(1)(2)(3)

(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.

(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock

edge. FA5 value should be stored inside AccessTime register bits field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal

direction on the GPMC data bus.

256

Timing Requirements and Switching Characteristics

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AM5728 Datasheet(PDF) 256 Page - Texas Instruments

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