DM385 datasheet(140/281 Pages) TI

140 / 281 page

DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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When the device is a PCI Express Root Complex (RC), the PCIE Subsystem can be reset by software

through the PRCM. Software should ensure that there are no ongoing PCIE transactions before asserting

this reset by first taking the PCIE Subsystem into the IDLE state. After bringing the PCIE Subsystem out

of reset, bus enumeration should be performed again and should treat all Endpoints (EP) as if they had

just been connected.

When the device is a PCI Express Endpoint (EP), the PCIE Subsystem will generate an interrupt when an

in-band reset is received. Software should process this interrupt by putting the PCIE Subsystem in the

IDLE state and then asserting the PCIE local reset through the PRCM.

All device level resets mentioned in the previous sections, except Test Reset, will also reset the PCIE

Subsystem. Therefore, the PCIE peripheral should issue a Hot Reset to all downstream devices and re-

enumerate the bus upon coming out of reset.

For more detailed information on reset isolation procedures, see the PCIe Reset Isolation section of the

Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical

Reference Manual.

7.3.13 EMAC Switch Reset Isolation

The device supports reset isolation for the Ethernet Switch (EMAC Switch) only when clock sourced from

SERDES. The other clocking source options do not provide RESET Isolation. This allows the device to

undergo all resets listed in Section 7.3.1, System-Level Reset Sources, with the exception of POR Reset,

without disrupting the Ethernet Switch or the traffic being routed through the switch during the reset

condition. The following reset types can optionally provide an EMAC Switch reset isolation by setting the

ISO_CONTROL bit in the RESET_ISO Control Module register to a "1":

•

External Warm Reset

•

Emulation Warm Reset

•

Watchdog Reset

•

Software Global Cold Reset

•

Software Global Warm Reset

When one of above resets occurs and the Ethernet Switch (EMAC Switch) is programmed to be isolated:

•

The switch function of the EMAC Switch and the PLL embedded in the SERDES Module (which

provides the reference clocks to the EMAC Switch) will not be reset.

•

Several Control Module registers are not reset. For more details, see the description of the

RESET_ISO register in the Control Module chapter of the device-specific Technical Reference Manual

•

The pin multiplexing of some of the EMAC Switch pins is unaffected. For more details, see the

description of the RESET_ISO register in the Control Module chapter in the device-specific Technical

Reference Manual.

The EMAC Switch is always reset when:

•

One of the above resets occurs and the Ethernet Switch is programmed to be “not isolated”

•

A POR Reset occurs

7.3.14 RSTOUT_WD_OUT Pin

The RSTOUT_WD_OUT pin reflects device reset status and is de-asserted (high) when the device is out

reset. This output will always be asserted when a Watchdog Timer reset (Watchdog Reset) occurs. In

addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR

and/or RESET is asserted; therefore, an external pullup/pulldown can be used to set the state of this pin

(high/low) while POR and/or RESET is asserted. For more detailed information on external PUs/PDs, see

Section 4.5.1, Pullup/Pulldown Resistors.

If the BTMODE[11] pin is latched as a "0" at the rising edge of POR or RESET, then RSTOUT_WD_OUT

is also asserted when any of the below resets occur:

140

Power, Reset, Clocking, and Interrupts

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