DM385 datasheet(142/281 Pages) TI

142 / 281 page

DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

www.ti.com

NOTE

The reset pin state is after all the power supplies are ramped up and stable. The state is not

not ensured during power-up sequencing.

Upon coming out of reset, the ARM Cortex-A8 starts executing code from the internal Boot

ROM. The Boot ROM code modifies the PINCNTLx registers to configure the associated

pins for the chosen primary and backup Bootmodes.

7.3.18 Reset Electrical Data/Timing

NOTE

For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).

Table 7-8. Timing Requirements for Reset (see Figure 7-5 and Figure 7-6)

OPP100

NO.

UNIT

MIN

MAX

tw(RESET)

Pulse duration, POR low or RESET low

12P(1)

POR

2P(2)

Setup time, BTMODE[15:0] pins valid before POR high or

tsu(BOOT)

RESET high

RESET

2P(2)

th(BOOT)

Hold time, BTMODE[15:0] pins valid after POR high or RESET high

(1)

The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET) requirement.

(2)

P = 1/(DEV Clock) frequency in ns.

Table 7-9. Switching Characteristics Over Recommended Operating Conditions During Reset

(see Figure 7-6)

OPP100

NO.

PARAMETER

UNIT

MIN

MAX

td(RSTL-

Delay time, RESET low or POR low to all I/Os entering their reset state

IORST)

td(RSTH-

Delay time, RESET high or POR high to all I/Os exiting their reset state

IOFUNC)

RESET assertion tw(RESET)

≥ 30P

td(RSTH-

Delay time, RESET high to RSTOUT_WD_OUT high(1)(2)

RSTOUTH)

RESET assertion tw(RESET)

32P -

< 30P

tw(RESET)

td(PORH-

Delay time, POR high to RSTOUT_WD_OUT high(1)(2)

12500P

RSTOUTH)

td(RSTL-

Delay time, RESET low to RSTOUT_WD_OUT Hi-Z(1)(2)

RSTOUTZ)

td(PORH-

Delay time, POR high to RSTOUT_WD_OUT driven based on latched BTMODE[11]

RSTOUTL)

value(1)(2)

td(RSTH-

Delay time, RESET high to RSTOUT_WD_OUT driven based on latched BTMODE[11]

RSTOUTD)

value(1)(2)

(1)

For more detailed information on RSTOUT_WD_OUT pin behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.

(2)

P = 1/(DEV Clock) frequency in ns.

142

Power, Reset, Clocking, and Interrupts

Submit Documentation Feedback

Product Folder Links: DM385 DM388

DM385 Datasheet(PDF) 142 Page - Texas Instruments

DM385 Datasheet(HTML) 142 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL