DM385 datasheet(234/281 Pages) TI

234 / 281 page

DDR3

Controller

DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

www.ti.com

Table 8-64. PCB Stackup Specifications

NO.

PARAMETER

MIN

TYP

MAX

UNIT

PCB routing/plane layers

Signal routing layers

Full ground reference layers under DDR3 routing region(1)

Full 1.35-V/1.5-V power reference layers under the DDR3 routing region(1)

Number of reference plane cuts allowed within DDR routing region(2)

Number of layers between DDR3 routing layer and reference plane(3)

PCB feature spacing

Mils

PCB trace width, w

Mils

PCB BGA escape via pad size(4)

Mils

PCB BGA escape via hole size

Mils

Processor BGA pad size

0.4

Single-ended impedance, Zo

Ω

Impedance control(5)

Z-5

Z+5

Ω

(1)

Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer

return current as the trace routes switch routing layers.

(2)

No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts

create large return current paths which can lead to excessive crosstalk and EMI radiation.

(3)

Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.

(4)

An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available

for power routing. An 18-mil pad is required for minimum layer count escape.

(5)

Z is the nominal singled-ended impedance selected for the PCB specified by item 13.

8.13.3.6 Placement

Figure 8-58 shows the required placement for the processor as well as the DDR3 devices. The

dimensions for this figure are defined in Table 8-65. The placement does not restrict the side of the PCB

on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace

lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3

devices are omitted from the placement.

Figure 8-58. Placement Specifications

234

Peripheral Information and Timings

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