LM49352 datasheet(34/106 Pages) TI

34 / 106 page

300 kHz

MCLK

_> 50 MHz

_ 50 MHz

OSCILLATOR

INTERNAL

PORT2_CLK

AUDIO

PORT 1

PMC

Stereo DAC

MIXER

Stereo ADC

PLL

% DAC

PMC, DAC, ADC divides by 1, 1.5, 2,

2.5 ==> 128

% ADC

% PMC

AUDIO

PORT 2

PORT1_CLK

_ 50 MHz

% 1/2

Cycle

% 1/2

Cycle

Half Cycle divides by 1, 1.5, 2, 2.5 ==> 32

LM49352

SNAS467E – MARCH 2009 – REVISED MARCH 2013

www.ti.com

Table 6. DAC Clock Requirements

DAC Sample Rate

Clock Required at A

(kHz)

(OSR = 128)

(OSR = 125)

(OSR = 64)

(OSR = 32)

2.048 MHz

2 MHz

1.024 MHz

0.512 MHz

11.025

2.8224 MHz

2.75625 MHz

1.4112 MHz

0.7056 MHz

3.072 MHz

3 MHz

1.536 MHz

0.768 MHz

4.096 MHz

4 MHz

2.048 MHz

1.024 MHz

22.05

5.6448 MHz

5.5125 MHz

2.8224 MHz

1.4112 MHz

6.144 MHz

6 MHz

3.072 MHz

1.536 MHz

8.192 MHz

8 MHz

4.096 MHz

2.048MHz

44.1

11.2896 MHz

11.025 MHz

5.6448 MHz

2.8224 MHz

12.288 MHz

12 MHz

6.144 MHz

3.072 MHz

24.576 MHz

24 MHz

12.288 MHz

6.144 MHz

Table 7. ADC Clock Requirements

ADC Sample Rate

Clock Required at B

(kHz)

(OSR = 128)

(OSR = 125)

2.048 MHz

2 MHz

11.025

2.8224 MHz

2.75625 MHz

3.072 MHz

3 MHz

4.096 MHz

4 MHz

22.05

5.6448 MHz

5.5125 MHz

6.144 MHz

6 MHz

8.192 MHz

8 MHz

44.1

11.2896 MHz

11.025 MHz

12.288 MHz

12 MHz

Figure 57. Internal Clock Network

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