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LM49352 Datasheet(PDF) 27 Page - Texas Instruments

Part # LM49352
Description  Boomer Mono Class D Audio Codec Subsystem with Ground Referenced Headphone Amplifiers, Earpiece Driver, and Audio DSP
PDF  106 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LM49352 Datasheet(HTML) 27 Page - Texas Instruments

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SDA
SCL
1
8
2
3
7
6
5
8
10
4
9
1
7
ack from slave
ack from slave
w
rs
r
stop
ack from slave
ack from master
repeated start
data from slave
start
w ack
ack
rs
r ack
ack stop
start
SCL
SDA
MSB Chip Address LSB
slave address =
00110102
register address = 0x00h
MSB Register 0x00h LSB
MSB
Data
LSB
MSB Chip Address LSB
slave address =
00110102
register 0x00h data
ack
ack
ack
ack
start
MSB Chip Address LSB
w
ack
MSB Register 0x02h LSB
ack
MSB
Data
LSB
ack
stop
ack from slave
ack from slave
ack from slave
SCL
SDA
start
slave address =
00110102
w
ack
register address = 0x02h
ack
ack
register 0x02h data
stop
ADR6
Bit7
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
R/W
bit0
MSB
LSB
I
2
C SLAVE address (chip address)
LM49352
www.ti.com
SNAS467E – MARCH 2009 – REVISED MARCH 2013
Figure 53. I2C Chip Address
Register changes take effect at the SCL rising edge during the last ACK from slave.
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
Figure 54. Example I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
the Read Cycle waveform.
Figure 55. Example I2C Read Cycle
Figure 56. I2C Timing Diagram
I
2C TIMING PARAMETERS
Limit
Symbol
Parameter
Units
Min
Typ
Max
Copyright © 2009–2013, Texas Instruments Incorporated
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