LM49352 datasheet(33/106 Pages) TI

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LM49352

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SNAS467E – MARCH 2009 – REVISED MARCH 2013

PMC Clocks Register

This register is used to control the LM49352's Basic Power Management Clock:

Table 4. PMC_SETUP (0x01h)

Bits

Field

Description

1:0

PMC_CLK_SEL

This selects the source of the PMC input clock.

PMC_CLK_SEL

PMC Input Clock Source

MCLK (Default divide is 40.5)

Internal 300kHz Oscillator

DAC SOURCE CLOCK

ADC SOURCE CLOCK

PMC Clock Divide Register

This register is used to control the LM49352's Power Management Circuit Clock Divider:

Table 5. PMC_SETUP (0x02h)

Bits

Field

Description

7:0

PMC_CLK_DIV

This programs the half cycle divider that precedes the PMC. The PMC should run from a 300kHz

clock. The default of this divider is 0x50h (divide by 40.5) to get a

≈300kHz PMC clock from a 12MHz

or 12.288MHz MCLK.

Program this divider with the required division, multiplied by 2, and subtract 1.

PMC_CLK_DIV

Divide by

00000000

00000001

00000010

1.5

00000011

00000100

2.5

00000101

—

11111101

126

11111110

127.5

11111111

128

LM49352 Clock Network

(Refer to Figure 57)

The audio DAC and ADC operate at a clock frequency of 2*OSR*fS where OSR is the oversampling ratio and fS

is the sampling frequency of the DAC or ADC. The DAC can operate at three different OSR settings (128, 125,

64). The ADC can operate at two different OSR settings (128, 125). For example, if the stereo DAC or ADC is

set at OSR = 128, a 12.288MHz clock is required for 48kHz data. If a 12.288MHz clock is not available, then the

internal PLL can be used to generate the desired clock frequency. Otherwise, if a 12.288MHz is available, the

PLL can be bypassed to reduce power consumption. The DAC clock divider or ADC clock divider can also be

used to generate the correct clock. If an 18.432 MHz clock is available, the DAC or ADC clock divider could be

set to 1.5 in order to generate a 12.288MHz clock from 18.432MHz without using a PLL.

The DAC path clock (DAC_SOURCE_CLK) and ADC path clock (ADC_SOURCE_CLK) can be driven directly by

the MCLK input, the PORT1_CLK input, the PORT2_CLK input, or PLL output.

For instances where a PLL must be used, the PLL input clock can come from three sources. The clock input to

the PLL can come from the MCLK input, the PORT1_CLK input, or the PORT2_CLK input.

The LM49352's Power Management Circuit (PMC) requires a clock that is independent from the DAC or ADC. It

is recommended to provide a

≈300kHz clock at Point C. The PMC clock divider is available to generate the

correct clock to the PMC block. The PMC clock path can be driven directly by the MCLK input, the internal

300kHz oscillator, the DAC_SOURCE_CLK, or the ADC_SOURCE_CLK.

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