LM49352 datasheet(54/106 Pages) TI

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LM49352

SNAS467E – MARCH 2009 – REVISED MARCH 2013

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Table 36. BASIC_SETUP (0x50h/0x60h) (continued)

Bits

Field

Description

SYNC_INVERT

If this bit is set the SYNC is inverted before the receiver and transmitter.

SYNC_INVERT

SYNC ORIENTATION

SYNC Low = Left, SYNC High = Right

SYNC Low = Right, SYNC High = Left

Table 37. CLK_GEN_1 (0x51h/0x61h)

Bits

Field

Description

5:0

HALF_CYCLE_CLK_DI This programs the half-cycle divider that generates the master clocks in the audio port. The default of

this divider is 0x00, i.e. bypassed.

Program this divider with the required division multiplied by 2, and subtract 1.

HALF_CYCLE_CLK_DIV

Divides By

000000

BYPASS

000001

000010

1.5

000011

—

111101

111110

31.5

11111

CLOCK_SEL

This selects the clock source of the master mode Audio Port Clock generator's half-cycle divider.

0 = DAC_SOURCE_CLK

1 = ADC_SOURCE_CLK

Table 38. CLK_GEN_1 (0x52h/62h)

Bits

Field

Description

2:0

SYNTH_NUM

Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in master

mode.

SYNTH_NUM

Numerator

000

SYNTH_DENOM (1/1)

001

100/SYNTH_DENOM

010

96/SYNTH_DENOM

011

80/SYNTH_DENOM

100

72/SYNTH_DENOM

101

64/SYNTH_DENOM

110

48/SYNTH_DENOM

111

0/SYNTH_DENOM

SYNTH_DENOM

Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or Port 2 clock in master

mode.

SYNTH_DENOM

Denominator

128

125

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