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LM49352 Datasheet(PDF) 52 Page - Texas Instruments |
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LM49352 Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 106 page ![]() 23 22 21 20 2 1 0 23 22 21 20 2 1 0 23 I2S_CLK I2S_SDO/ I2S_SDI I2S_SYNC Left Word Right Word 23 22 21 2 1 0 23 22 21 2 1 0 I2S_CLK I2S_SDO/ I2S_SDI I2S_SYNC Left Word Right Word LM49352 SNAS467E – MARCH 2009 – REVISED MARCH 2013 www.ti.com Table 35. Decimator Input Select (0x45h) Bits Field Description 1:0 L_SEL This selects which input is fed to the left ADC's decimator input. L_SEL Selected Input 00 None 01 PORT1_RX_L 10 PORT2_RX_L 11 DAC_INTERP_L 3:2 R_SEL This selects which input is fed to the right ADC's decimator input. R_SEL Selected Input 00 None 01 PORT1_RX_R 10 PORT2_RX_R 11 DAC_INTERP_R 5:4 MXR_CLK_SEL This selects sets the source of the Digital Mixer Clock. The 'Auto' setting will automatically select the source with the highest clock frequency. If the DAC interpolator output (DAC_OSR_L or DAC_OSR_R) is selected, then MXR_CLK_SEL should be set to '10'. MXR_CLK_SEL Selected Input 00 Auto 01 MCLK 10 DAC 11 ADC Audio Port Control Registers Figure 62. I2S Serial Data Format (24 bit example) Figure 63. Left Justified Data Format (24 bit example) 52 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM49352 |
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