LM49352 datasheet(26/106 Pages) TI

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SDA

SCL

START condition

STO

P condition

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LM49352

SNAS467E – MARCH 2009 – REVISED MARCH 2013

www.ti.com

SYSTEM CONTROL

Method 1. I2C Compatible Interface

2C SIGNALS

In I2C mode the LM49352 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal

SDA. Both these signals need a pull-up resistor according to I2C specification. The I2C slave address for

LM49352 is 00110102.

2C DATA VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when SCL is LOW.

Figure 51. I2C Signals: Data Validity

2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.

The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

Figure 52. I2C Start and Stop Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eight bit which is a data direction bit (R/W). The LM49352 address is 00110102. For the eighth bit, a “0” indicates

a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

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