TAS5630B

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SLES217D – NOVEMBER 2010 – REVISED MARCH 2015

7.3.5 Pin-to-Pin Short-Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is

shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the

demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is

performed at startup, that is, when VDD is supplied; consequently, a short to either GND_X or PVDD_X after

system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on

the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the

startup sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step

ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from

OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC

filter. The typical duration is <15 ms/

μF. While the PPSC detection is in progress, SD is kept low, and the device

does not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and

SD is released, a device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and

PBTL output configurations; the detection is not performed in SE mode. To make sure the PPSC detection

system is not tripped, it is recommended not to insert resistive load between OUT_X and GND_X or PVDD_X.

7.3.6 Overtemperature Protection

The two different package options have individual overtemperature protection schemes.

PHD Package:

The TAS5630B PHD package option has a three-level temperature-protection system that asserts an active-low

warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device

junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the

device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)

state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.

Thereafter, the device resumes normal operation. For highest reliability, the RESET should not be asserted until

OTW1 has cleared.

DKD Package:

The TAS5630B DKD package option has a two-level temperature-protection system that asserts an active-low

warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction

temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs

being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the

OTE latch, RESET must be asserted. It is recommended to wait until OTW has cleared before asserting RESET.

Thereafter, the device resumes normal operation.

7.3.7 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5630B fully protect the device in any power-up/down and brownout

situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are

fully operational when the GVDD_X and VDD supply voltages reach the levels stated in Electrical

Characteristics. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP

threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-

impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply

voltages have increased above the UVP threshold.

7.3.8 Device Reset

When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance

(Hi-Z) state.

In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables

weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when

asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD

output; that is, SD is forced high. A rising-edge transition on reset input allows the device to resume operation

after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms

after the falling edge of SD.

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