TAS5630B

SLES217D – NOVEMBER 2010 – REVISED MARCH 2015

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10.2 Layout Example

Note T1: PVDD bulk decoupling capacitors C60–C64 should be as close as possible to the PVDD_X and GND_X

pins; the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins

and without going through vias. No vias or traces should be blocking the current path.

Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins. This is valid for C60, C61, C62, and C63.

Note T3: Heat sink must have a good connection to PCB ground.

Note T4: Output filter capacitors must be linear in the applied voltage range, preferably metal film types.

Figure 23. Printed Circuit Board – Top Layer

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