PIC18F010 datasheet(129/176 Pages) MICROCHIP

129 / 176 page

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 127

PIC18F010/020

RETURN

Return from Subroutine

Syntax:

[ label ]

RETURN [s]

Operands:

∈ [0,1]

Operation:

(TOS)

→ PC,

if s = 1

(WS)

→ W,

(STATUSS)

→ STATUS,

(BSRS)

→ BSR,

PCLATU, PCLATH are unchanged

Status Affected:

None

Encoding:

0000

0001

001s

Description:

Return from subroutine. The

stack is popped and the top of the

stack (TOS) is loaded into the

program counter. If ’s’ = 1, the

contents of the shadow registers

WS, STATUSS and BSRS are

loaded into their corresponding

registers, WREG, STATUS and

BSR. If ’s’ = 0, no update of

these registers occurs (default).

Words:

Cycles:

Q Cycle Activity:

Decode

operation

Process

Data

Pop PC from

stack

operation

Example:

RETURN

After Call

TOS

RETURN FAST

Before Instruction

WRG

0x04

STATUS =

0x00

BSR

0x00

After Instruction

WREG

0x04

STATUS =

0x00

BSR

0x00

TOS

RLCF

Rotate Left f through Carry

Syntax:

[ label ] RLCF

f [ ,d [,a] ]

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f<n>)

→ dest<n+1>,

(f<7>)

→ C,

(C)

→ dest<0>

Status Affected:

C,N,Z

Encoding:

0011

01da

ffff

Description:

The contents of register 'f' are

rotated one bit to the left through

the Carry Flag. If 'd' is 0 the result is

placed in WREG. If 'd' is 1 the

result is stored back in register 'f'

(default). If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, the Bank

will be selected as per the BSR

value.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

RLCF

REG, W

Before Instruction

REG

1110 0110

After Instruction

REG

1110 0110

WREG

1100 1100

PIC18F010 Datasheet(PDF) 129 Page - Microchip Technology

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