PIC18F010 datasheet(132/176 Pages) MICROCHIP

132 / 176 page

PIC18F010/020

DS41142A-page 130

Preliminary

 2001 Microchip Technology Inc.

SLEEP

Enter SLEEP mode

Syntax:

[ label ] SLEEP

Operands:

None

Operation:

00h

→ WDT,

→ WDT postscaler,

→ TO,

→ PD

Status Affected:

TO, PD

Encoding:

0000

0011

Description:

The power-down status bit (PD) is

cleared. The time-out status bit

(TO) is set. Watchdog Timer and

its postscaler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

Words:

Cycles:

Q Cycle Activity:

Decode

operation

Process

Data

Go to

sleep

Example:

SLEEP

Before Instruction

TO =?

PD =?

After Instruction

TO =1 †

PD =0

† If WDT causes wake-up, this bit is cleared.

SUBFWB

Subtract f from WREG with borrow

Syntax:

[ label ] SUBFWB f [ ,d [,a] ]

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(WREG) – (f) – (C)

→ dest

Status Affected:

N,OV, C, DC, Z

Encoding:

0101

01da

ffff

Description:

Subtract register 'f' and carry flag

(borrow) from WREG (2’s comple-

ment method). If 'd' is 0, the result

is stored in WREG. If 'd' is 1, the

result is stored in register 'f'

(default) . If ’a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ’a’ is 1, the Bank

will be selected as per the BSR

value.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

PIC18F010 Datasheet(PDF) 132 Page - Microchip Technology

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