EN

IN

BIAS

GND

OUT

10 PF Ceramic

10 PF

Ceramic

1 PF

GND

GND

LP38856-x.x

LP38856

SNVS336F – JUNE 2006 – REVISED AUGUST 2015

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP38856 can provide 3-A output current with 240-mV dropout voltage (typical). The bias voltage must be in

capacitor on the bias pin must be at least 1

μF.

8.2 Typical Application

Figure 23. LP38856 Typical Application

8.2.1 Design Requirements

For LP38856 typical applications, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETERS

VALUE

Bias voltage

3 V to 5.5 V

Input voltage

Output voltage

0.8 V or 1.2 V

Output current

3 A (maximum)

Bias capacitor

1 µF (minimum)

Input capacitor

10 µF (minimum)

Output capacitor

10 uF (minimum)

8.2.2 Detailed Design Procedure

8.2.2.1 External Capacitors

To assure regulator stability, capacitors are required on the IN, OUT, and BIAS pins as shown in Figure 23.

8.2.2.1.1

Output Capacitor

A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can

be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the device

and returned to the device ground pin with a clean analog ground.

Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide

sufficient capacitance over temperature.

12

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