ML6440 datasheet(11/18 Pages) MICRO-LINEAR

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ML6440

internal data register low (D[7:0]=0) which defaults to

automatic combing of NTSC/CCIR601 composite video.

The Y+C/CV selection bit, D7, controls whether Y+C or CV

format is the source for the comb filter. Setting this bit low

selects the composite input pins, which is combed by

default. Setting the bit high selects the Y+C inputs as the

source for video (see bypass section). This source is not

combed and the Y+C inputs are not activated until the S/P

pin is rising-edge triggered.

Adaption thresholds 2 through 0 are D6 through D4,

respectively. These set the adaption behavior from

automatic (D[6:4]=000) to one of seven settings ranging

from fine tuning of computer graphics to photographic

images. See Table 4.

Comb modes 1 and 0, (D3 and D2, respectively) are used

to enable and disable adaption separately on Y and C

data. For NTSC, if D[3:2]=<00>, then Y is adaptive and C

is always combed. For NTSC, if D[3:2]=<01>, both Y and

C are adaptive. For PAL, if D[3:2]=<00>, then both Y and

C are adaptive. For PAL, if D[3:2]=<01>, then Y is

adaptive and C is combed. For NTSC and PAL, if

D[3:2]=<10>, then Y and C are forced to comb mode. For

NTSC and PAL, if D[3:2]=<11>, then both Y and C are in

bandsplit filtering mode only. See Table 5.

The D1 bit sets the choice of data rates between CCIR601

and Square pixel. CCIR601 is active low. Square pixel is

active high. The last bit, D0, select the standard, NTSC or

PAL. NTSC is active low. PAL is active high. See Table 2.

The remaining pin function controls are independent of

the data register: CLK, RST, and OE. The CLK pin requires

a clock at the rates listed in Table 2. Its duty cycle must

meet the duration minimum for high and low.

The RST pin resets the comb logic including the internal

data register on active low but does not clear the line

delays. This part requires a timed reset pulse. On power

up or at any time a return to automatic combing of NTSC/

CCIR601 composite video is required the reset pin must

have been high for at least 5 micro seconds. Then taken

low for at least one micro second before returning high

again to resume normal operation. Neither pulse width

nor rise and fall times are critical.

In most applications a microprocessor will be available to

provide timing and control waveforms. It will provide this

reset pulse and if needed set the appropriate comb filter

mode. In non processor systems an R C network can

provide this reset pulse. See Figure 5.

CHROMA AND LUMA BYPASS OPERATION

This mode can be activated by setting the internal bit

D7 = 1 either through the serial or parallel programming

modes. Once the register is set (D7 = 1), the comb filter

will look at the inputs for luma on the CV[7:0] pins for a

luma bypass to the outputs of the Y[7:0] pins respectively;

as well as inputs for chroma on the CI/DI[7:0] pins for a

chroma bypass to the outputs of the C[7:0] pins

respectively. The comb filter will continue to look at the

inputs as long as D7 is set high.

Data presented to the inputs (CI/DI[7:0]) is not interrupted

in the color processing path when S/P is held high or low.

Therefore, it is recommended that S/P activity be limited to

sync or blanking intervals in the video to avoid unwanted

visual artifacts during register programming.

Clock Timing

Figure 6 depicts digital video input and output timing for

valid data.

FUNCTIONAL DESCRIPTION (Continued)

Y OR C DATA

60%

20ns

15ns

0ns

Y OR C DATA

Y/C OUTPUT

CV INPUT

13.5MHz CLOCK

CV DATA

40%

CV DATA

Figure 6: Clock Timing

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