VIN

GND

Loop 1

Loop 2

VOUT

High

di/dt

LMZ22005

www.ti.com

SNVS686J – MARCH 2011 – REVISED AUGUST 2015

10 Layout

10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a

DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in

the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.

Good layout can be implemented by following a few simple design rules. A good example layout is shown in

Figure 54.

1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout as

shown in Figure 52. The high current loops that do not overlap have high di/dt content that will cause

pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input

and output capacitor should consist of a localized top side plane that connects to the PGND exposed pad

(EP).

2. Have a single point ground.

The ground connections for the feedback, soft-start, and enable components should be routed to the AGND

pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not

properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple

behavior. Additionally provide the single point ground connection from pin 4 (AGND) to EP/PGND.

3. Minimize trace length to the FB pin.

pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces from

4. Make input and output bus connections as wide as possible.

This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize

voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing

so will correct for voltage drops and provide optimum output accuracy.

5. Provide adequate device heat-sinking.

Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.

If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to

inner layer heat-spreading ground planes. For best results use a 6 × 10 via array with a minimum via

diameter of 8 mils thermal vias spaced 39 mils (1.0 mm). Ensure enough copper area is used for heat-

sinking to keep the junction temperature below 125°C.

10.2 Layout Examples

Figure 52. Critical Current Loops to Minimize

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