MT9V024 datasheet(52/62 Pages) ONSEMI

52 / 62 page

MT9V024_DSRev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC, 2015.

MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

Propagation Delays for PIXCLK and Data Out Signals

The pixel clock is inverted and delayed relative to the master clock. The relative delay

from the master clock (SYSCLK) rising edge to both the pixel clock (PIXCLK) falling edge

and the data output transition is typically 7ns. Note that the falling edge of the pixel

clock occurs at approximately the same time as the data output transitions. See Table 16

on page 46 for data setup and hold times.

Figure 38:

Propagation Delays for PIXCLK and Data Out Signals

Propagation Delays for FRAME_VALID and LINE_VALID Signals

The LV and FV signals change on the same rising master clock edge as the data output.

The LV goes HIGH on the same rising master clock edge as the output of the first valid

pixel's data and returns LOW on the same master clock rising edge as the end of the

output of the last valid pixel's data.

As shown in the “Output Data Timing” on page 9, FV goes HIGH 143 pixel clocks before

the first LV goes HIGH. It returns LOW 23 pixel clocks after the last LV goes LOW.

Figure 39:

Propagation Delays for FRAME_VALID and LINE_VALID Signals

tPD

tPLHP

tHD

tSD

SYSCLK

PIXCLK

DOUT(9:0)

PIXCLK

FRAME_VALID

LINE_VALID

tPFLF

tPFLR

PIXCLK

FRAME_VALID

LINE_VALID

MT9V024 Datasheet(PDF) 52 Page - ON Semiconductor