MT9V024 datasheet(17/62 Pages) ONSEMI

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MT9V024_DSRev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC, 2015.

MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor

Serial Bus Description

Sequence

A typical READ or WRITE sequence begins by the master sending a start bit. After the

start bit, the master sends the slave device’s 8-bit address. The last bit of the address

determines if the request is a read or a write, where a “0” indicates a WRITE and a “1”

indicates a READ. The slave device acknowledges its address by sending an acknowledge

bit back to the master.

If the request was a WRITE, the master then transfers the 8-bit register address to which

a WRITE should take place. The slave sends an acknowledge bit to indicate that the

with the slave sending an acknowledge bit after each 8 bits. The MT9V024 uses 16-bit

data for its internal registers, thus requiring two 8-bit transfers to write to one register.

After 16 bits are transferred, the register address is automatically incremented, so that

the next 16 bits are written to the next register address. The master stops writing by

sending a start or stop bit.

A typical READ sequence is executed as follows. First the master sends the write mode

slave address and 8-bit register address, just as in the write request. The master then

sends a start bit and the read mode slave address. The master then clocks out the register

data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The

transfer is stopped when the master sends a no-acknowledge bit. The MT9V024 allows

for 8-bit data transfers through the two-wire serial interface by writing (or reading) the

most significant 8 bits to the register and then writing (or reading) the least significant 8

bits to byte-wise address register (0x0F0).

Bus Idle State

The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-

ated with a start bit, and the bus is released with a stop bit. Only the master can generate

the start and stop bits.

Data Bit Transfer

One data bit is transferred during each clock pulse. The two-wire serial interface clock

pulse is provided by the master. The data must be stable during the HIGH period of the

serial clock—it can only change when the two-wire serial interface clock is LOW. Data is

transferred 8 bits at a time, followed by an acknowledge bit.

Table 4:

Slave Address Modes

{S_CTRL_ADR1, S_CTRL_ADR0}

Slave Address

Write/Read Mode

0x90

Write

0x91

Read

0x98

Write

0x99

Read

0xB0

Write

0xB1

Read

0xB8

Write

0xB9

Read

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