MT9V024 datasheet(45/62 Pages) ONSEMI

45 / 62 page

MT9V024_DSRev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC, 2015.

MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor

Feature Description

LINE_VALID

By setting bit 2 and 3 of R0x72, the LV signal can get three different output formats. The

formats for reading out four rows and two vertical blanking rows are shown in Figure 35.

In the last format, the LV signal is the XOR between the continuous LV signal and the FV

signal.

Figure 35:

Different LINE_VALID Formats

LVDS Serial (Stand-Alone/Stereo) Output

The LVDS interface allows for the streaming of sensor data serially to a standard off-the-

shelf deserializer up to eight meters away from the sensor. The pixels (and controls) are

packeted—12-bit packets for stand-alone mode and 18-bit packets for stereoscopy

mode. All serial signaling (CLK and data) is LVDS. The LVDS serial output could either be

data from a single sensor (stand-alone) or stream-merged data from two sensors (self

and its stereoscopic slave pair). The appendices describe in detail the topologies for

both stand-alone and stereoscopic modes.

There are two standard deserializers that can be used. One for a stand-alone sensor

stream and the other from a stereoscopic stream. The deserializer attached to a stand-

alone sensor is able to reproduce the standard parallel output (8-bit pixel data, LV, FV,

and PIXCLK). The deserializer attached to a stereoscopic sensor is able to reproduce 8-

bit pixel data from each sensor (with embedded LV and FV) and pixel-clk. An additional

(simple) piece of logic is required to extract LV and FV from the 8-bit pixel data. Irrespec-

tive of the mode (stereoscopy/stand-alone), LV and FV are always embedded in the pixel

data.

In stereoscopic mode, the two sensors run in lock-step, implying all state machines are

in the same state at any given time. This is ensured by the sensor-pair getting their sys-

clks and sys-resets in the same instance. Configuration writes through the two-wire

serial interface are done in such a way that both sensors can get their configuration

updates at once. The inter-sensor serial link is designed in such a way that once the slave

PLL locks and the data-dly, shft-clk-dly and stream-latency-sel are configured, the

master sensor streams valid stereo content irrespective of any variation voltage and/or

temperature as long as it is within specification. The configuration values of data-dly,

shft-clk-dly and stream-latency-sel are either predetermined from the board-layout or

can be empirically determined by reading back the stereo-error flag. This flag is asserted

when the two sensor streams are not in sync when merged. The combo_reg is used for

out-of-sync diagnosis.

Default

FRAME_VALID

LINE_VALID

Continuously

FRAME_VALID

LINE_VALID

XOR

FRAME_VALID

LINE_VALID

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