MT9V024 datasheet(14/62 Pages) ONSEMI

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MT9V024_DSRev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC, 2015.

MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor

Output Data Format

Output Data Timing

The data output of the MT9V024 is synchronized with the PIXCLK output. When

LINE_VALID (LV) is HIGH, one 10-bit pixel datum is output every PIXCLK period.

Figure 8:

Timing Example of Pixel Data

The PIXCLK is a nominally inverted version of the master clock (SYSCLK). This allows

PIXCLK to be used as a clock to latch the data. However, when column bin 2 is enabled,

the PIXCLK is HIGH for one complete master clock master period and then LOW for one

complete master clock period; when column bin 4 is enabled, the PIXCLK is HIGH for

two complete master clock periods and then LOW for two complete master clock

periods. It is continuously enabled, even during the blanking period. Setting R0x72

bit[4] = 1 causes the MT9V024 to invert the polarity of the PIXCLK.

The parameters P1, A, Q, and P2 in Figure 9 are defined in Table 2.

Figure 9:

Row Timing and FRAME_VALID/LINE_VALID Signals

Table 2:

Frame Time

Parameter

Name

Equation

Default Timing at 26.66 MHz

AActive data time

Context A: R0x04

Context B: R0xCC

752 pixel clocks

= 752 master

= 28.20s

Frame start blanking

Context A: R0x05 - 23

Context B: R0xCD - 23

71 pixel clocks

= 71master

= 2.66s

Frame end blanking

23 (fixed)

23 pixel clocks

= 23 master

= 0.86s

Horizontal blanking

Context A: R0x05

Context B: R0xCD

94 pixel clocks

= 94 master

= 3.52s

LINE_VALID

PIXCLK

DOUT(9:0)

(9:0)

Pn-1

(9:0)

Valid Image Data

Blanking

...

Number of master clocks

FRAME_VALID

LINE_VALID

...

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