TPS65276VRHHT datasheet(28/43 Pages) TI

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N: Not Acknowledge

A: Acknowledge

S: Start

P: Stop

Sr: Repeated Start

System Host

Chip

7-Bit Slave Address

Register1 Address

A Sr

7-Bit Slave Address

Data Byte

N P

7-Bit Slave Address

Data Byte

A P

TPS65276V

SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014

www.ti.com

TPS65276V I

2C Update Sequence

The TPS65276V requires a start condition, a valid I2C address, a register address byte, and a data byte for a

single update. After the receipt of each byte, TPS65276V device acknowledges by pulling the SDA line low

during the high period of a single clock pulse. A valid I2C address selects the TPS65276V. TPS65276V performs

an update on the falling edge of the LSB byte.

When the TPS65276V is in hardware shutdown (EN1 and EN2 pin tied to ground) the device can not be updated

via the I2C interface. Conversely, the I2C interface is fully functional during software shutdown (EN1 and EN2 bit

= 0).

Figure 38. I2C Write Data Format

Figure 39. I2C Read Data Format

Table 2. Register Addresses

NAME

BITS

ADDRESS

Vout1_SEL

0x00H

Vout2_SEL

0x01H

Vout1_COM

0x02H

Vout2_COM

0x03H

Sys_STATUS

0x04H

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