TPS70102PWPR datasheet(23/42 Pages) TI

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VOUT2

VIN1

VIN2

SEQ

VOUT1

VSENSE1

PG1

MR2

RESET

MR1

VSENSE2

VOUT2

TPS701xxPWP

(Fixed Output Option)

VOUT1

MR1

0.1

µF

RESET

µF

0.1

µF

MR2

>2 V

<0.7 V

250 k

Ω

83%

95%

120ms

VOUT2

VOUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

SEQ

95%

83%

NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.

(see Note A)

TPS70145, TPS70148

TPS70151, TPS70158

TPS70102

www.ti.com

SLVS222I – DECEMBER 1999 – REVISED AUGUST 2010

APPLICATION INFORMATION

Sequencing Timing Diagrams

This section provides a number of timing diagrams

showing

how

this

device

functions

different

configurations.

Application condition: MR2 is tied to PG1, VIN1 and

VIN2 are tied to the same input voltage, the SEQ pin

is tied to logic low and the device is toggled with the

enable (EN) function.

When the device is enabled (EN is pulled low), VOUT1

turns on first and VOUT2 remains off until VOUT1

reaches approximately 83% of its regulated output

voltage. At that time, VOUT2 is turned on. When VOUT1

reaches 95% of its regulated output, PG1 turns on

(active high). Since MR2 is connected to PG1 for this

application, it follows PG1. When VOUT2 reaches 95%

of its regulated voltage, RESET switches to high

voltage level after a 120ms delay (see Figure 40).

Figure 40. Timing when SEQ = Low

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