TPS70102PWPR datasheet(27/42 Pages) TI

27 / 42 page

RESET

VOUT2

VIN1

VIN2

SEQ

VOUT1

VSENSE1

PG1

MR2

RESET

MR1

VSENSE2

VOUT2

VOUT1

MR1

0.1

µF

0.1

µF

MR2

TPS701xxPWP

(Fixed Output Option)

>2 V

<0.7 V

83%

95%

83%

95%

120ms

ENABLE

VOUT2

VOUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

SEQUENCE

NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.

(see Note A)

VOUT2 faults out

TPS70145, TPS70148

TPS70151, TPS70158

TPS70102

www.ti.com

SLVS222I – DECEMBER 1999 – REVISED AUGUST 2010

Application condition: MR2 is tied to PG1, VIN1 and

VIN2 are tied to same input voltage, the SEQ is tied to

logic high, the device is enabled, and VOUT2 faults

out.

VOUT2 begins to power up when the device is enabled

(EN is pulled low). When VOUT2 reaches 83% of its

regulated voltage, VOUT1 begins to power up. When

VOUT1 reaches 95% of its regulated voltage, PG1

turns on and RESET switches to high voltage level

after a 120ms delay. When VOUT2 faults out, VOUT1 is

powered down because SEQ is high. PG1 is tied to

MR2 and both change state to logic low. RESET

goes low when VOUT2 faults out (see Figure 44).

Figure 44. Timing when VOUT2 Faults Out

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TPS70102PWPR Datasheet(PDF) 27 Page - Texas Instruments

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