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SM5847AF Datasheet(PDF) 9 Page - Nippon Precision Circuits Inc |
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SM5847AF Datasheet(HTML) 9 Page - Nippon Precision Circuits Inc |
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9 / 30 page  SM5847AF NIPPON PRECISION CIRCUITS—9 Reset timing (RSTN) VDD = VDDAC = 3.00 to 5.25 V, VSS = VSSAC = 0 V, Ta = −40 to 85 °C Output timing (CKO, BCKO, WCKO, DOL, DOR, DG) VDD = VDDAC = 4.75 to 5.25 V, VSS = VSSAC = 0 V, Ta = −40 to 70 °C, CL = 50 pF P arameter Symbol Condition Rating Unit min 1 1. tMCK is equal to 1/fXTI or 1/fOSC. For example, tRST = 54 ns when fXTI = 37 MHz. typ m a x RSTN LO W -level reset pulsewidth tRST 2tMCK –– ns P arameter Symbol Condition Rating Unit min typ m a x XTI falling edge to CKO falling edge delay tXTO 4–9 ns V DD = V DDAC = 3.00 to 5.25 V, Ta = −40 to 85 °C 4– 1 1 ns B C K O falling edge to W C K O , DOL, DOR, DG delay tBDO −4– 2 ns B C K O rising edge to W C K O falling edge tWO H Output mode: 8fs OMD = HIGH (fs = 192 kHz) External clock input: XTI = 27 ns (37 MHz), CKSLN = HIGH (192fs) Divider ratio: 1 C K DV1 = CKDV2 = LOW Output data length: 24 bits O W1N = OW2N = LOW 8–– ns W C K O falling edge to BCKO rising edge tWO S 8–– ns B C K O per iod tOBCY 27 – – ns B C K O HIGH-level pulsewidth tOBCH 7–– ns B C K O L OW -level pulsewidth tOBCL 7–– ns DOL, DOR setup time tODS 7–– ns DOL, DOR hold time tODH 7–– ns B C K O rising edge to W C K O falling edge tWO H Output mode: 4fs OMD = LOW (fs = 192 kHz) External clock input: XTI = 27 ns (37 MHz), CKSLN = HIGH (192fs) Divider ratio: 1 C K DV1 = CKDV2 = LOW Output data length: 24 bits O W1N = OW2N = LOW 17 – – ns W C K O falling edge to BCKO rising edge tWO S 17 – – ns B C K O per iod tOBCY 54 – – ns B C K O HIGH-level pulsewidth tOBCH 18 – – ns B C K O L OW -level pulsewidth tOBCL 18 – – ns DOL, DOR setup time tODS 18 – – ns DOL, DOR hold time tODH 18 – – ns 1.5V RSTN tRST |
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