SM5847AF datasheet(17/30 Pages) NPC

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SM5847AF

NIPPON PRECISION CIRCUITS—17

Internal System Clock (XTI, XTO, CKO, CKSLN, CKDV1, CKDV2)

The SM5847AF supports two system clock frequen-

cies selected by CKSLN, 192fs and 256fs, where fs

is the sampling frequency.

The master clock can be provided either by a crystal

oscillator connected between XTI and XTO, or by an

external master clock input on XTI. Note that the

feedback resistor required by the oscillator option is

not built-in. External components should be selected

to match the crystal oscillator element. Note also that

XTO must be left open (ﬂoating) for the external

master clock input option.

Note that even though it is necessary that the master

clock and LRCI clock (sampling frequency fs) be in

sync, it is not necessary that they be exactly in-phase

(see jitter-free mode description).

The SM5847AF features independent divide-by 1, 2,

or 4counter, selected by CKDV1 and CKDV2. This

provides the 192fs or 256fs system clock with the

necessary divider ratios to support master clocks

with frequencies of 768fs, 384fs, 192fs, 1024fs,

512fs or 256fs.

Normal sampling frequencies 32 kHz, 44.1 kHz,

48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz

are supported. However, some combinations of sam-

pling frequency and master clock frequency are not

supported, as follows.

768fs and 1024fs at 88.2 and 96 kHz

768fs, 384fs, 1024fs, 512fs, and 256fs at

176.4 kHz

768fs, 384fs, 1024fs, 512fs and 256fs at 192 kHz

Note also that the internal crystal oscillator circuit

cannot operate at frequencies

≥ 50 MHz. The master

clock input on XTI is output on CKO.

Master clock stop operation

The master clock is input after power is applied.

But if, after the XTI and LRCI clocks are input and

power-ON reset occurs with all-zero input audio

data, the master clock input on XTI is held either

HIGH or LOW level, operation effectively stops.

Note also that a reset signal is not accepted when the

master clock and LRCI clock stop.

Table 4. Internal system clock select

CKSLN

System clock

L O W

256fs

HIGH

192fs

Table 5. System clock frequency divider ratio select

CKD V 1

CKD V 2

Divider

ratio

Master clock

L O W

192fs, 256fs

L O W

HIGH

–

Prohibited mode

HIGH

L O W

768fs, 1024fs

HIGH

384fs,512fs

Figure 3. Crystal oscillator connection

Figure 4. External clock connection

XTAL

XTI

XTO

CKO

Divider

Master Clock

Buffer output

SM5847AF

XTI

XTO

CKO

Divider

Master Clock

Buffer output

SM5847AF

External Clock

XTO : open

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