3-58

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Characteristics

Sym

Min

Max

Units

Test Conditions

1

D

P

L

L

#2

C4b output clock period

213

244

275

ns

85 pF Load

2C4b output clock width (HIGH)

85

159

ns

3C4b output clock width (LOW)

116

122

ns

4C4b output clock rise time

6

ns

85 pF Load

5C4b clock output fall time

6

ns

85 pF Load

6

Frame pulse output delay

(HIGH to LOW) from C4b

013

ns

85 pF Load

7

Frame pulse output delay

(LOW to HIGH) from C4b

08

ns

85 pF Load

8

Frame pulse (F0b) width

225

245

ns

9

C4o delay - LOW to HIGH

015

ns

10

C4o delay - HIGH to LOW

020

ns

11

C4b to C2o delay (LOW to

HIGH)

03

ns

12

C4b to C2o delay (HIGH to

LOW)

06

ns

13

C2o clock period

457

488

519

ns

85 pF Load

14

C2o clock width ( HIGH )

207

280

ns

15

C2o clock width ( LOW )

238

244

ns

16

C2o clock rise time

6

ns

85 pF Load

17

C2o clock fall time

6

ns

85 pF Load

18

C2o delay - LOW to HIGH

-5

2

ns

19

C2o delay - HIGH to LOW

05

7

ns