MT8941AP datasheet(7/18 Pages) MITEL

7 / 18 page

CMOS

MT8941

3-49

When MS3 is HIGH, DPLL #2 operates in any of the

major modes selected by MS0 and MS1. When MS3

is LOW, it overrides the major mode selected and

DPLL#2 accepts an external clock of 4.096 MHz on

C4b (pin 13) to provide the 2.048 MHz clocks (C2o

and

C2o)

and

the

kHz

frame

pulse

(F0b)

compatible with the ST-BUS format. The mode select

bit MS2 controls the direction of the signal on F0b

(pin 6).

When MS2 is LOW, the F0b pin is an 8 kHz frame

pulse input. This input is effective only when MS3 is

also LOW and pin C4b is fed by a 4.096 MHz clock,

which has a proper phase relationship with the

signal on F0b (refer Figure 18). Otherwise, the input

on pin F0b will have no bearing on the operation of

DPLL #2, unless it is in FREE-RUN mode as

selected by MS0 and MS1. In FREE-RUN

mode,

the input on F0b is treated the

same way as the

C8Kb input is in NORMAL mode. The frequency of

the signal on F0b should be 16 kHz for DPLL #2 to

lock and generate the ST-BUS compatible clocks at

4.096 MHz and 2.048 MHz.

When MS2 is HIGH, the F0b pin provides the frame

pulse output compatible with the ST-BUS format and

locked to the internal or external input signal as

determined by the other mode select pins.

Table 4 summarizes the modes of the two DPLL. It

should be noted that each of the major modes

selected for DPLL #2 can have any of the minor

modes, although some of the combinations are

Table 5. Functions of the Bidirectional Signals

in Each Mode

Notes:

: Input

: Output

: “don’t care” input. Connect to VDD or VSS.

Mode

F0b

(kHz)

C4b

(MHz)

C8Kb

(kHz)

CVb

(MHz)

i:8

i:4.096

i:X

o:1.544

i:X

o:4.096

i:8

o:1.544

o:8

i:4.096

i:X

o:1.544

o:8

o:4.096

i:8

o:1.544

i:8

i:4.096

i:X

i:1.544

i:X

o:4.096

o:8

i:1.544

o:8

i:4.096

i:X

i:1.544

o:8

o:4.096

o:8

i:1.544

i:8

i:4.096

i:X

o:1.544

i:16

o:4.096

i:X

o:1.544

o:8

i:4.096

i:X

o:1.544

o:8

o:4.096

i:X

o:1.544

i:8

i:4.096

i:X

i:2.408

i:X

o:4.096

o:8

i:2.408

o:8

i:4.096

i:X

i:2.408

o:8

o:4.096

o:8

i:2.408

functionally similar. The required operation of both

DPLL #1 and DPLL #2 must be considered when

determining MS0-MS3.

The

direction

and

frequency

each

the

bidirectional signals are listed in Table 5 for each of

the given modes in Table 4.

Jitter Performance and Lock-in Range

The output jitter of a DPLL is composed of the

intrinsic jitter, measured when no jitter is present at

the input, and the output jitter resulting from jitter on

the input signal. The spectrum of the intrinsic jitter

for both DPLLs of the MT8941 is shown in Figure 5.

The typical peak-to-peak value for this jitter is

0.07UI. The transfer function, which is the ratio of

the output jitter to the input jitter (both measured at a

particular frequency), is shown in Figure 6 for DPLL

#1 and Figure 7 for DPLL #2. The transfer function

is measured when the peak-to-peak amplitude of the

sinusoidal input jitter conforms to the following:

10 Hz - 100 Hz

: 13.6 µs

100 Hz - 10 kHz

: 20 dB / decade roll-off

> 10 kHz

: 97.2 ns

The ability of a DPLL to phase-lock the input signal

to the reference signal and to remain locked

depends upon its lock-in range. The lock-in range of

the DPLL is specified in terms of the maximum

frequency variation in the 8 kHz reference signal. It

is also directly affected by the oscillator frequency

tolerance. Table 6 lists different values for the lock-in

range and the corresponding oscillator frequency

tolerance for DPLL #1 and DPLL #2.

The smaller

the tolerance value, the larger the lock-in range.

The T1 and CEPT standards specify that, for free

running equipment, the output clock tolerance must

be less than or equal to ±32ppm and ±50ppm

respectively. This requirement restricts the

Table 6. Lock-in Range vs. Oscillator Frequency

Tolerance

* Please refer to the section on “Jitter Performance and Lock-in

Range” for recommended oscillator tolerances for DPLL #1 & #2.

Oscillator Clock*

Tolerance (±ppm)

Lock-in Range (±Hz)

DPLL #1

DPLL #2

2.55

1.91

2.51

1.87

2.43

1.79

2.33

1.69

2.19

1.55

100

1.79

1.15

150

1.39

.75

175

1.19

.55

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