MT8941AP datasheet(5/18 Pages) MITEL

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CMOS

MT8941

3-47

at 8 kHz to generate T1 (1.544 MHz) clock.

For

DPLL #2, the divisions are set at 8 and 256 to

provide the CEPT/ST-BUS clock at 2.048 MHz

synchronized to the falling edge of the input signal (8

kHz).

The master clock source is specified to be

12.352 MHz for DPLL #1 and 16.384 MHz for DPLL

#2 over the entire temperature range of operation.

The inputs MS0 to MS3 are used to select the

operating mode of the MT8941, see Tables 1 to 4.

All the outputs are controlled to the high impedance

condition by their respective enable controls.

The

uncommitted NAND gate is available for use in

applications involving Mitel’s MT8976/ MH89760 (T1

Interfaces)

and

MT8979/MH89790

(CEPT

Interfaces).

Modes of Operation

The operation of the MT8941 is categorized into

major modes and minor modes. The major modes

are defined for both DPLLs by the mode select pins

MS0 and MS1.

The minor modes are selected by

pins MS2 and MS3 and are applicable only to DPLL

#2. There are no minor modes for DPLL #1.

Major modes of DPLL #1

DPLL #1 can be operated in three major modes as

selected by MS0 and MS1 (Table 1). When MS1 is

LOW, it is in NORMAL mode, which provides a T1

(1.544 MHz) clock signal locked to the falling edge

of the input frame

pulse F0i

(8 kHz).

DPLL #1

requires a master clock input of 12.352 MHz (C12i).

In the second and third major modes (MS1 is HIGH),

DPLL #1 is set to DIVIDE an external 1.544 MHz or

2.048 MHz signal applied at CVb (pin 21).

The

division can be set by MS0 to be either 193 (LOW) or

256 (HIGH).

In these modes, the 8 kHz output at

C8Kb is connected internally to DPLL #2, which

operates in SINGLE CLOCK mode.

Major modes of DPLL #2

There are four major modes for DPLL #2 selectable

by MS0 and MS1, as shown in Table 2. In all these

modes DPLL #2 provides the CEPT PCM30 timing,

and the ST-BUS clock and framing signals.

In NORMAL mode, DPLL #2 provides the CEPT/ST-

BUS compatible timing signals locked to the falling

edge of the 8 kHz input signal (C8Kb).

These

signals are 4.096 MHz (C4o and

C4b) and 2.048

MHz (C2o and C2o) clocks, and the 8 kHz frame

pulse (F0b) derived from the 16.384 MHz master

clock.

This mode can be the same as the FREE-

RUN mode if the C8Kb pin is tied to VDD or VSS.

Note:

X: indicates don’t care

Table 1. Major Modes of DPLL #1

Table 2. Major Modes of DPLL #2

Table 3. Minor Modes of DPLL #2

In FREE-RUN mode, DPLL #2 generates the stand-

alone CEPT and ST-BUS timing and framing signals

with no external inputs except the master clock set at

16.384 MHz. The DPLL makes no correction in this

configuration and provides the timing signals without

any jitter.

Mode of

Operation

Function

NORMAL

Provides the T1 (1.544 MHz) clock

synchronized to the falling edge of

the input frame pulse (F0i).

DIVIDE-1

DPLL #1 divides the CVb input by

193. The divided output is

connected to DPLL #2.

DIVIDE-2

DPLL #1 divides the CVb input by

256. The divided output is

connected to DPLL #2.

Mode of

Operation

Function

NORMAL

Provides CEPT/ST-BUS timing

signals locked to the falling edge of

the 8 kHz input signal at C8Kb.

FREE-RUN

Provides CEPT/ST-BUS timing and

framing signals with no external

inputs, except the master clock.

SINGLE

CLOCK-1

Provides CEPT/ST-BUS timing

signals locked to the falling edge of

the 8 kHz internal signal provided by

DPLL #1.

SINGLE

CLOCK-2

Provides CEPT/ST-BUS timing

signals locked to the falling edge of

the 8 kHz internal signal provided by

DPLL #1.

Functional Description

Provides CEPT/ST-BUS 4.096 MHz and 2.048

MHz clocks and 8kHz frame pulse depending on

the major mode selected.

Provides CEPT/ST-BUS 4.096 MHz & 2.048 MHz

clocks depending on the major mode selected

while F0b acts as an input. However, the input on

F0b has no effect on the operation of DPLL #2

unless it is in FREE-RUN mode.

Overrides the major mode selected and accepts

properly phase related external 4.096 MHz clock

and 8 kHz frame pulse to provide the ST-BUS

compatible clock at 2.048 MHz.

Overrides the major mode selected and accepts a

4.096 MHz external clock to provide the ST-BUS

clock and frame pulse at 2.048 MHz and 8 kHz,

respectively.

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