CMOS

MT8941

3-59

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

* Please review the section on "Jitter Performance and Lock-in Range".

Figure 17 - Master Clock Inputs

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Figure 18 - External Inputs on C4b and F0b for the DPLL #2

Characteristics

Sym

Min

Max

Units

Test Conditions

1

C

L

O

C

K

S

Master clocks input rise time

10

ns

2

Master clocks input fall time

10

ns

3

Master clock period

(12.352MHz)*

80.943

80.958

80.974

ns

For DPLL #1, while operating to

provide the T1 clock signal.

4

Master clock period

(16.384MHz)*

61.023

61.035

61.046

ns

For DPLL #2, while operating to

provide the CEPT and ST-BUS

timing signals.

5

Duty Cycle of master clocks

45

50

55

%

6

Lock-in Range

DPLL #1

DPLL #2

-2.33

-1.69

+2.33

+1.69

Hz

With the Master frequency

tolerance at ±32 ppm.

Characteristics

Sym

Min

Max

Units

Test Conditions

1F0b input pulse width (LOW)

244

ns

2C4b input clock period

244

ns

3

Frame pulse (F0b) setup time

50

ns

4

Frame pulse (F0b) hold time

25

ns

Master clock

inputs

2.4 V

1.5 V

0.4 V

F0b

C4b