MT8971B/72B

9-116

The C-channel is used for transferring control and

status information between the DNIC and the

system. The Control and Diagnostics Registers are

accessed through the C-channel. They contain

information to control the DNIC and carry out the

diagnostics as well as the HK bit to be transmitted on

the line as described in Tables 4 and 5. Bits 0 and 1

of the C-channel select between the Control and

Diagnostics Register. If these bits are 0, 0 then the

C-channel information is written to the Control

Register (Table 4).

If they are 0, 1 the C-

written to the Diagnostics Register (Table 5).

The Diagnostics Register Reset bit (bit 2) of the

Control Register determines the reset state of the

Diagnostics Register. If, on writing to the Control

Register, this bit is set to logic “0”, the Diagnostics

Register will be reset coincident with the frame

pulse. When this bit is logic “1”, the Diagnostics

Register will not be reset.

In order to use the

diagnostic features, the Diagnostics Register must

be continuously written to. The output C-channel

sends status information from the Status Register to

the system along with the received HK bit as shown

in Table 6.

In MOD mode, the CD port is no longer an ST-BUS

but is a serial bit stream operating at the bit rate

selected. It continues to transfer the C-channel but

the D-channel and the HK bit no longer exist. DUAL

port operation must be used in MOD mode. The C-

channel is clocked in and out of the CD port by TCK

Table 4. Control Register

Notes:

Œ

Suggested use of ATTACK:

-At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms.

-At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms.



When bits 4-7 of the Control Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,

depending upon the status of bit-3.

Bit

Name

Description

0

Reg Sel-1

Register Select-1. Must be set to ’0’ to select the Control Register.

1

Reg Sel-2

Register Select-2. Must be set to ’0’ to select the Control Register.

2

DRR

Diagnostics Register Reset. Writing a "0" to this bit will cause a diagnostics register reset

to occur coincident with the next frame pulse as in the MT8972A. When this bit is a logic

"1", the Diagnostics Register will not be reset.

3

BRS

Bit Rate Select. When set to ’0’ selects 80 kbit/s. When set to ’1’, selects 160 kbit/s.

4DINB



D-Channel in B Timeslot. When ’0’, the D-channel bits (D0 or D0 and D1) corresponding

to the selected bit rate (80 or 160 kbit/s) are transmitted during the normal D-channel bit

times. When set to ’1’, the entire D-channel (D0-D7) is transmitted during the B1-channel

timeslot on the line providing a 64 kbit/s D-channel link.

5

PSEN



Prescrambler/Deprescrambler Enable. When set to ’1’, the data prescrambler and

deprescrambler are enabled. When set to ’0’, the data prescrambler and deprescrambler

are disabled.

6ATTACK



Convergence Speedup. When set to ’1’, the echo canceller will converge to the reflection

coefficient much faster. Used on power-up for fast convergence.

canceller will require the normal amount of time to converge to a reflection coefficient.

7

TxHK



Transmit Housekeeping. When set to ’0’, logic zero is transmitted over the line as

Housekeeping Bit. When set to ’1’, logic one is transmitted over the line as

Housekeeping Bit.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

Reg Sel-1

Reg Sel-2

DRR

BRS

DINB

PSEN

ATTACK

TxHK

Default Mode Selection (Refer to Table 4a)