MT8971B/72B

9-122

† Timing is over recommended temperature & power supply voltages.

* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

.

† Timing is over recommended temperature & power supply voltages.

* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Notes:

1)

When operating as a SLAVE the C4 clock has a 40% duty cycle.

2)

When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e.,

Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

1

I

N

P

U

T

S

Input Voltage

5.0

2

Input Current

-10

+10

µ

3

Input Impedance

20

40

k

Ω

4

Crystal/Clock Frequency

10.24

MHz

5

Crystal/Clock Tolerance

-100

0

+100

ppm

6a

Crystal/Clock Duty Cycle

Œ

40

50

60

%

6b

Crystal/Clock Duty Cycle

Œ

45

50

55

%

Recommended at max./

7

Crystal/Clock Loading

33

50

pF

8

O

U

T

P

U

T

S

Output Capacitance

8pF

9

Load Resistance

500

100

Ω

k

Ω

10

Load Capacitance

0.1

20

pF

µF

11

Output Voltage

3.2

4.3

4.6

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

1C4 Clock Period

244

ns

2C4 Clock Width High or Low

90

122

150

ns

In Master Mode - Note 1

3

Frame Pulse Setup Time

50

ns

4

Frame Pulse Hold Time

50

ns

5

Frame Pulse Width

172

244

ns

6

-15

+15

ns

Note 2

Channel 31

Bit 0

Channel 0

Bit 7

Channel 0

Bit 6

F0b

C4

ST-BUS

BIT CELLS